# Propagation delay in case of synchronous counters

Consider 4 bit counter as shown below:- Here suppose we consider propagation delay of each flip flop =2ns and propagation delay of each AND gate is 3ns, then what will be the total propagation delay?

As all flip flops get the same clock, we add the propagation delay of flip flop only once but my doubt is whether to add the propagation delay of AND gate only once or twice ?

So will the propagation delay be 2+3 =5ns or 2+3+3=8ns ?

• Good start. What do you think it is, and why? – user_1818839 Sep 17 '17 at 14:49
• Do you understand about Setup time and Hold time? – analogsystemsrf Sep 17 '17 at 15:10
• This is a synchronous circuit, so there is no offset between computation stages. the propagation delay is the clock to output time of the FF. There is no combinational circuit between the FF's Q and the counter's Q outputs. It would be totally different if each Q would drive the next stage's C. This would be called asynchronous counter. – Paebbels Sep 17 '17 at 15:44
• The input to the last flip flop depends on the output of the previous AND gate. So why should we not add AND gate delays? – Zephyr Sep 17 '17 at 17:26
• @Brian Drummond, Please explain the answer if possible. I think that it should be 2+3+3 because the last flip flops input depends on the output of 2 AND gates, so we must add the propagation delay of both AND gates. – Zephyr Sep 17 '17 at 18:09

## 1 Answer

The propagation delay will be 2ns because that is the time between the changing input (clock) and outputs (Q0-Q3). Propagation delay of the AND gates not relevant because their outputs should be stable when the flip flips are clocked. However they may limit the maximum frequency that the counter can be clocked at, because their outputs need to be correct when the clock occurs.

The JK input to the fourth flip flop (FF3) is determined by the states of Q0-Q2. These outputs are stable 2ns after the clock, but then pass through up to two AND gates. If the next clock occurs too early then FF3's JK input will not have had enough time to stabilize and the counter will malfunction.

The total delay between clock input and FF3 JK input is up to 2+3+3 = 8ns. Therefore the minimum acceptable time between clocks is 8ns + JK setup time. So long as this timing is met the counter should work correctly, and the propagation delay will be 2ns because Q outputs only change in response to clock inputs.

• Thanks for answering. Yes, I understand that flip flops propagation delay would be 2ns only and we don't add them because this is a synchronous counter. Suppose we want to find the frequency of the clock signal for correct working of the counter. Then it would be 1/8ns and not 1/2ns right ? As total propagation delay would be 8ns because this is a series synchronous counter. – Zephyr Sep 17 '17 at 18:53
• Propagation delay is the time between an input changing and response of the output(s), in this case 2ns. However (assuming 0ns setup time) the time period between clocks must be at least 8ns or the counter will malfunction. Therefore the maximum clock frequency is 1/8ns = 125MHz. Practical example:- 74F160 Tpd CP->Q = 3.5ns, maximum clock frequency 80MHz = 12.5ns – Bruce Abbott Sep 17 '17 at 20:26
• According to you "propagation delay is the time between an input changing and response of output". So shouldn't it be max(2,3) = 3ns. As it will take 3ns for AND gate to produce output after a change in it's input. – Zephyr Sep 17 '17 at 20:30
• On each clock the Q outputs change first, then the AND gates change. The AND gates only set up the conditions for the next count, and have no direct involvement in the clock (input) to Q (output) delay. – Bruce Abbott Sep 17 '17 at 20:43
• Yes. In a simple counter the clock is the only input, so propagation delays must be relative to it. A more complex device might have other inputs which have their own propagation delays. – Bruce Abbott Sep 17 '17 at 22:21