# Propagation delay in case of synchronous counters

Consider 4 bit counter as shown below:- Here suppose we consider propagation delay of each flip flop =2ns and propagation delay of each AND gate is 3ns, then what will be the total propagation delay?

As all flip flops get the same clock, we add the propagation delay of flip flop only once but my doubt is whether to add the propagation delay of AND gate only once or twice ?

So will the propagation delay be 2+3 =5ns or 2+3+3=8ns ?

• Good start. What do you think it is, and why?
– user16324
Sep 17, 2017 at 14:49
• Do you understand about Setup time and Hold time? Sep 17, 2017 at 15:10
• This is a synchronous circuit, so there is no offset between computation stages. the propagation delay is the clock to output time of the FF. There is no combinational circuit between the FF's Q and the counter's Q outputs. It would be totally different if each Q would drive the next stage's C. This would be called asynchronous counter. Sep 17, 2017 at 15:44
• The input to the last flip flop depends on the output of the previous AND gate. So why should we not add AND gate delays? Sep 17, 2017 at 17:26
• @Brian Drummond, Please explain the answer if possible. I think that it should be 2+3+3 because the last flip flops input depends on the output of 2 AND gates, so we must add the propagation delay of both AND gates. Sep 17, 2017 at 18:09