I'm trying to analyze the Sparkfun Logic Level converter found here:


A rough schematic is shown below:


simulate this circuit – Schematic created using CircuitLab

Now, I've looked at the application note mentioned on Sparkfun's page, and I understood most of it in regards to how it shifts levels, but I'm having trouble understanding the third part going from the high logic voltage to the lower logic voltage. I searched for some similar questions on the site, but teh answers that I found didn't seem to explain this part well.

My question is how does it shift the logic level from the high logic to the low logic? The app note says that when voltage on the high side, it utilizes the diode between the drain and substrate; at this point, the substrate (body) is at 3.3 V, so when the high input is 0 volts, the 'diode' conducts, dropping the voltage at the low port to 0, turning on the diode, further dropping the voltage. When the 'diode' conducts, why does it drop the source pin (connected to the body/substrate) down from 3.3 to 0? I would have thought that it stayed the same voltage at 3.3 V.


1 Answer 1


One characteristic of MOSFETs is that the drain pin can act as a source (and vice versa) depending upon the voltages applied to the terminals. That is exploited in this circuit. When the source pin is more positive than the drain pin it will act as a drain with the drain pin acting as a source. If the source pin is more than 0.7V positive than the drain the body diode will conduct but that doesn't interfere with the FET action.

When there is a low level on the high-voltage port and the voltage between the gate and the drain pin will exceeds the threshold voltage of the device the device will start to conduct. The drain pin acts as a source pin in this case. The positive bias causes the MOSFET to conduct from source to drain and pull down the voltage on the low-voltage port down to a very low voltage (only millivolts above the voltage on the high-voltage port. I measured a BSS138 and discovered that the threshold voltage in this inverse mode is very similar to that in normal mode - I couldn't find that detail in any data sheets.

The method of fabricating MOSFETs creates the diode (referred to as a body-diode) as a side-effect - in this case the body diode does not affect operation significantly except for the case where the voltage on the high-voltage port is low enough to cause the body diode to conduct but there is not enough voltage difference between the gate and the drain pin to turn the device on - in this case the low-voltage port will be at a voltage abut 600mV above that on the other port.

As commented by @Michael Karas the threshold voltage needs to be significantly lower than the low voltage source to operate correctly.

Also as commented by @Michael Kara the physical construction of discrete devices is not symmetric but for basic analysis of the circuit it can be treated as such with the body diode in parallel.

  • \$\begingroup\$ Thanks for the answer. So, in this case it's due to the positive bias between the gate and the drain that causes a depletion region to form thereby allowing conductivity between source and drain, pulling down the voltage. Strange way to think about it since textbooks (at least mine) always refers to the bias between gate and source. \$\endgroup\$ Commented Sep 18, 2017 at 16:04
  • \$\begingroup\$ @user101402, your textbooks should be telling you about common source, common gate, and common drain configurations the same way they told you about common emitter, common base, and common collector configurations for BJTs. But they might do that pretty quickly before moving on to differential pairs and other topics. \$\endgroup\$
    – The Photon
    Commented Sep 18, 2017 at 16:55
  • 1
    \$\begingroup\$ I think you got things a little wrong Kevin. When the high voltage side goes low it is not the Drain being puiled low which causes the N-FET to turn on. Instead what happens is that the conduction through the body diode is what pulls the N-FET source down. This increases the N-FET gate to source voltage and enables it to start to turn on. As the N-FET starts to turn on it then causes the ON FET to short out across the body diode allowing the low on the high voltage side to be seen on the low voltage side. \$\endgroup\$ Commented Sep 18, 2017 at 17:49
  • \$\begingroup\$ An additional comment is that my description above should make it clear why this type of level translator circuit needs to use an N-FET that has a Vgsth that is less than the low voltage side supply value minus the body diode drop. If the FET has a Vgsth of 4.5V it does not work in this type of circuit with a 3.3V low side voltage. \$\endgroup\$ Commented Sep 18, 2017 at 17:56
  • \$\begingroup\$ @MichaelKaras - No that is not correct. This circuit would work correctly even without the body diode. A MOSFET is almost symmetric in its fabrication - the terms Drain and Source are determined by the bias conditions. There are some integrated level shifters (eg LSF0204) where there is no body diode as the substrate is connected to the negative supply rail. You are correct in regard to the required threshold voltage - it can sometimes be tricky to find a device that works acceptably for 1.8V to 3.3v interface - a BSS138 is not adequate. \$\endgroup\$ Commented Sep 18, 2017 at 20:14

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