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So this is a schematic for an AVR Programmer seen here: http://www.sparkfun.com/products/9825

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On the bottom you will see a 74AC125 which is a Quad Buffer with Tri-State Outputs. I've seen quite a few buffers like this on programmers.....but im not exactly sure what they do? Im assuming whatever "CTL" is controls the "state" of the buffers.....but what exactly is the point? Why can't you wire it directly to whatever Port Line (Serial or w/e). Or does this have something to do with Impedance (Which Im not sure I STILL quite understand).

Is it because the Signals are coming out of the ATTINY2313 (or w/e MC is used) too fast and they need to be slowed down? I see this often when using a USB port of Serial Line....that one of these "Buffers" is used. What would happen if it wasn't there?

Or is this all just some sort of Serial Protocol Im guessing?

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3 Answers 3

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First, there's no need to assume anything. It's extremely easy to find a datasheet for this sort of part.

The schematic clearly shows the CTL signal going to the output enable inputs of the part. The signal must be low to allow the buffer to operate. When enabled, a low on the input produces a low on the output, and a high on the input produces a high on the output.

Generally, a bus buffer like the 74AC125 is used for improving drive capability. Some micros cannot source high current from their digital outputs, and need a buffer to effectively drive their loads.

Buffers can also be used for logic level shifting - your micro may be a 3.3V part, and your external logic may need 5V logic levels. A buffer takes care of this translation for you - the buffer can be powered from the higher rail, so that a 3.3V H input becomes a 5V H output.

A buffer also protects the digital output lines of the micro from external 'badness' (short circuits) - even though most micros do protect their I/O lines, it's much easier replacing a buffer IC than it is to replace and reprogram a micro.

In terms of delays, the buffer isn't like a memory buffer in the computing realm - it doesn't inherently store data so that it can be transmitted more slowly. It does introduce a propagation delay, so the output signal is delayed in time compared with the input signal (but at the same data rate) - a phase delay instead of a baud rate reduction, so to speak.

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  • \$\begingroup\$ I'm curious how would 74AC125 work with logic level translation. Wouldn't it just provide input voltage at the output too? \$\endgroup\$
    – AndrejaKo
    May 31, 2012 at 17:07
  • \$\begingroup\$ @andrejako It's a hypothetical answer (not applicable to OP) - if the buffer is on a 5V rail and is fed by 3.3V logic, it will translate. \$\endgroup\$
    – Adam Lawrence
    May 31, 2012 at 17:34
  • \$\begingroup\$ So from what I can see from the Datasheet it's taking low level inputs (from like .8 to 1.5) and outputting 0 volts, and High level inputs of 1.5 to 2 volts and giving out 5 volts? Is this incorrect? Is the main purpose in the Schematic I listed Probably increasing voltage to the outputs? or is it probably using it for Propagation Delay like you said? \$\endgroup\$
    – user3073
    May 31, 2012 at 19:52
  • \$\begingroup\$ @Sauron It depends on the status of the TARGET-PWR switch S1. If it's connecting to VCC, the buffer will output 3.3V for a H. Propagation delay is a consequence of using the buffer (and for applications like a programmer, not something deliberately designed in.) It's more likely for higher current capability than the micro can provide, and to shield the micro from external electrical faults (shorts, etc.) \$\endgroup\$
    – Adam Lawrence
    Jun 1, 2012 at 15:51
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    \$\begingroup\$ @Sauron The buffers tend to be designed with higher current-capability drivers than many low-power micros - stronger transistors, essentially. The buffer draws an extremely small current from the micro I/O line, and uses its own VCC supply to source higher current (sort of like an amplifier). \$\endgroup\$
    – Adam Lawrence
    Jun 3, 2012 at 22:36
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I think that the buffer is there to provide a little bit of isolation between the voltages of the programmer and the voltage of the target board. From schematic, we can see that the buffer can be powered from the target board or from the programmer. In case of small voltage differences lower than 0.5 V between the target board and the programmer's power supply, the buffer will stop current going from one power supply to another.

The other use is to enable or disable the output to the programming header. In order for programming to work, the programmer's microcontroller needs to sink current on the pin connected to the CTL line. What this allows us is to use the JP2 connector to work with programmer's microcontroller and since signals are shared between JP2 and JP3, the buffer allows us to use JP2 and not interfere with JP3 while using it.

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    \$\begingroup\$ Buffers are also oftentimes uses as the sacrificial lambs... if something goes wrong it's oftentimes a lot easier and less expensive to replace the buffer than the microcontroller doing the programming. \$\endgroup\$
    – akohlsmith
    May 31, 2012 at 22:18
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This programmer supports both (a) programming 5 V targets, and also (b) programming 3 V targets -- in particular, 3 V targets that are not 5 V tolerant. a b c

In this particular application, the 74ACT125 buffer provides logic level shifting. One side of the buffer is connected to MCU in the programmer (running at 5 V levels) and the other side of the buffer (and the VCC of the buffer) is connected to the cable leading to the target board. Some target boards run at 5 V, other target boards run at 3 V levels. (The 74ACT125 seems to be running slightly out of specification in this application -- I'm not sure why the designer didn't pick an alternatives such as the 74HC4050, TXB0104, or 74LVCC4245 ).

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