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I would like to add a !(SLEEP) line for this CMOS oscillator in a way that in case of low input on !(SLEEP) line, the output PWM line is constant low.

2 questions for the circuit:

  • In this case do I need to use Schmitt trigger for the AND gate?
  • Is there a simpler, more professional way to achieve this?

enter image description here

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    \$\begingroup\$ Why would you not just bring /SLEEP to pin 2 of IC2A? \$\endgroup\$
    – Trevor_G
    Sep 19, 2017 at 19:31

1 Answer 1

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I'd run the sleep line directly into pin 2 of IC2A instead of adding another AND gate. That way you retain the Schmidt trigger and don't add a race to IC2A for the clock line.

NOTE: You could also feed the /SLEEP signal to pin 6 on IC2B instead, but then the clock is still free running and when you wake it you can never know where you are in the clock cycle.

Addition: I'd also consider limiting the extents of R3 by adding another series resistor in there to ensure you can never get zero ohms when the pot is at one end or the other.

enter image description here

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    \$\begingroup\$ Thanks. I modified the schematics according to you answer and added a resistor. \$\endgroup\$ Sep 21, 2017 at 11:35

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