Apparently there is concern that github might fall off the face of the earth, so hopefully this intro can pass muster... There is a lot more detail in that linked thread than I can summarize adequately, but I think these are the important bits:
do you think that the pannel may be driven this way :
Display bottom line (32th) send 1 line of data (RGB+Clock) x64, strobe
A, up B, strobe A x31, down B strobe latch Display previous line up B,
strobe A, down B send 1 line of data (RGB+Clock) x64, strobe A, up B,
strobe A x30, down B ... and scan all 32 lines ?
I think the roles of pins : A : strobing pushes display one row down.
B : down, pushed row (by A strobe) is lit, down pushed row is black.
Clocking data set it on all rows. So for each scan, I clock the data,
and push only one lit row (with A and B). So I push down first row as
lit, and the remainings as black, so the "lit" row moves down.
There are code samples in there for driving a panel with an RPi. Timing is apparently also important but it's possible that I'm misreading exactly how, and I have not had time to really study it. I'm working on an FPGA panel driver but back-burnering implementing this feature for now.