I needed a VCCS so then I simulated the circuit below in LTSpice and it worked great. I also designed the PCB and produced it, solder it and it still works great. But I have a big problem!

When the input (positive input of the opamp) is left unconnected, and the load is connected, the opamp hugs the VPOS or VNEG rails (arbitrarly!) and the output current goes to 2.35A (I am lucky that I put that current limiting resistor so the current will never go above +/- 2.35 ampers.

enter image description here enter image description here enter image description here

I think this is because of the input offset voltage of the MP38 and the fact that with no input since it will be open loop...it hugs the supply rail (I do not understand why sometimes it goes to V+ and sometimes goes to V-).

So my questions are:

  1. Is what I said above the problem? or there is more to it?
  2. How to prevent this kind of behaviour (possibly with some schematics please!)
  3. What could I do better for this Circuit/PCB?

Would be this a solution (R1, 10k resistor pull-down parallel with input connector): enter image description here

  • \$\begingroup\$ I don't quite get why the + of the opamp would be left unconnected, it seems to have at least a connections to the output side, which bears the other question of why you did it that way and not try to follow the reference schematic of the datasheet \$\endgroup\$
    – PlasmaHH
    Sep 21, 2017 at 9:36
  • \$\begingroup\$ Add a pull-down resistor in parallel to your input connector. When a source is connected it serves no purpose, when unconnected it biases the input for 0V. \$\endgroup\$
    – sstobbe
    Sep 21, 2017 at 14:39
  • \$\begingroup\$ @sstobbe Doesn't a pull down resistor from input of the connector to ground make a voltage divider and screw the result? \$\endgroup\$
    – Dumbo
    Sep 21, 2017 at 20:03
  • \$\begingroup\$ Not if Ro of your voltage source is low. You can try it in spice add a resistor in parallel to Vin(2) \$\endgroup\$
    – sstobbe
    Sep 21, 2017 at 21:04
  • \$\begingroup\$ @sstobbe Please check the image I added, is this what you mean? \$\endgroup\$
    – Dumbo
    Sep 22, 2017 at 8:39

1 Answer 1


Without the input voltage applied the opamp is not in open loop. It still has feedback but the feedback has become positive instead of negative. I do not think offset has anything to do with this.

All 4 feedback resistors are 10 k so feedback to both inputs (inverting and non-inverting) is 1/2. If you disconnect the input source then the feedback to the non-inverting input changes to 1 so it "wins" when compared to the (still 1/2) feedback of the inverting input.

I disregard the fact that the negative feedback is from one side of the sense resistor and the positive feedback is coming from the other side. But since the voltage across the sense resistor is small I think I can safely do this.

A possible solution might be to apply the input voltage on the inverting input side and ground the left side of Rin1. That way when there is no input voltage source applied the negative feedback would increase (which is OK, I think) but the positive feedback stays at 1/2.

You might also have to swap the feedback signals around the sense resistor since you would be introducing the input voltage at the negative side now.

If possible, compare both situations in a simulator and see if that resolves the issue.

  • \$\begingroup\$ Thanks for the info. I am having a hard time understanding your possible solution...would it possible to add a schematic to your answer? \$\endgroup\$
    – Dumbo
    Sep 22, 2017 at 21:15
  • \$\begingroup\$ Sorry, too lazy. And the change is quite simple, first schematic: move Rin2 down to where Vin and Rin1 are. Move Vin and Rin1 up to where Rin2 is. If you really need a schematic then you draw it, edit your question and use the included schematic drawing tool. Then add a comment here under my answer that you did that (so I will get a notification) then I will come back, copy and change that schematic from your question and include it in my answer. \$\endgroup\$ Sep 22, 2017 at 21:27

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