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I am designing a circuit that measure the energy consumed from 50Hz AC supply (error must be < 1%), by measuring the voltage through potential divider; and current from shunt resistor. Then these two signals go to ADC inputs of microcontroller PIC18F46K80 to be multiplied and get the power.

The voltage signal enters a potential divider and an amplifier with DC offset and go to the ADC input. In current measurement circuit the difference between shunt terminals is amplified and then an amplifier with two feedback resistors (NMOS used to select between them to modify the gain) amplify its again. Then go to a DC offset stage after that to the ADC input.

The problem is when the phase change between current and voltage, the energy measurement error changed by 0.8% if the power factor of measured energy changed from 1 to 0.8L.

During my work in this circuit I had come with these notes:

1- Capacitive coupled noise (in the OPAMP negative input) could affect the measurement if the power factor is changed. But in this case I am sure it is not because I measure the RMS value in the ADC to check if there is a capacitive coupled noise or not.

2- The OPAMP is not 100% inverting, it has some parasitic effects on the phase of the signal that comes to it. It depends on the gain and other stuff.

3- I had some DC blocking capacitor that will make a phase shift (time delay), between voltage and current signal, this phase is very small but it affect the measurement accuracy.

The points 2&3, I have solved it by making small software delay between acquiring the signal of the voltage and the current to compensate for that phase shift/delay.

I have two circuits: The old one works perfect when the power factor change from 1 to 0.5L. But it suffered from aging of a capacitor as described here (Ceramic Capacitor Aging Stack Exchange). The accuracy had dropped after 2 months of operation. So I have modified the circuit (NEW ONE) by increasing the capacitors and some resistors to minimize the effect of the capacitor aging. But Now I couldn’t even have an acceptable result, though I have tried adding variable delays between reading the voltage and current from the ADC.

New Measurement Circuit Old Measurement Circuit

The Code:

//================== voltage measurement ==================== //
  set_adc_channel(VOLT_CHANNEL);                                               //voltage reading channel
  delay_us(3);                                                           //wait for ADC channel capacitor to charge
  voltage_binary = read_adc(); 
  delay_us(10);
  //================== current measurement =====================//
  set_adc_channel(Current_Channel);                                           //current reading channel
  delay_us(3);                                                             //wait for ADC channel capacitor to charge
  current_binary = read_adc();

Differences between two designs:

Item New Design/Old Design

C16 10uF/4.7uF

C7 100uF/47uF

OPAMP TL064ID/TL064INSR

D9 BAS70/BAV99S

Resistor Case Code 1608/2012

R38 100K/18.2K

R35 470K/82K

Sampling rate (Sample/Second) 3400/2700

The Question is: What else could affect the operation of the measurement when the power factor change?

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  • \$\begingroup\$ You could attach a scope and look at signals... \$\endgroup\$ – PlasmaHH Sep 21 '17 at 11:17
  • \$\begingroup\$ @PlasmaHH I have already did, nothing abnormal. The scope couldn't measure the phase shift between the two signals. \$\endgroup\$ – Ashraf Almubarak Sep 21 '17 at 11:25
  • \$\begingroup\$ How do you know then if it is there? If the scope can't see it, what can? \$\endgroup\$ – PlasmaHH Sep 21 '17 at 11:51
  • \$\begingroup\$ @PlasmaHH, I am not sure if it is there or not. I am not sure if there is a small phase shift (less than 1 degree) in the ADC inputs the scope will measure it. \$\endgroup\$ – Ashraf Almubarak Sep 21 '17 at 11:59
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Then these two signals go to ADC inputs of microcontroller PIC18F46K80 to be multiplied and get the power

It is unlikely that simultaneous sampling will be used so there will inherently be a phase error of one sample period.

The problem is when the phase change between current and voltage, the energy measurement error changed by 0.8% if the power factor of measured energy changed from 1 to 0.8L.

Yes, that sounds like the problem of not sampling simultaneously - close to unity PF the error due to this will be small and, as the phase angle gets bigger (lower PF) the error will increase.

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  • \$\begingroup\$ In the old one, it worked good when I have assembled the board, but after two months the aging of ceramic capacitor affected the performance. In the new one, I didn't have a good results from the beginning. \$\endgroup\$ – Ashraf Almubarak Sep 21 '17 at 12:04
  • \$\begingroup\$ Yes I read that but it still doesn't get over the fat that non-simultaneous sampling will create an error that progressively gets worse on non-unity power factors. \$\endgroup\$ – Andy aka Sep 21 '17 at 12:07
  • \$\begingroup\$ You are right. How about the effect of the OPAMP amplifier and DC blocking capacitor, are not going to compensate for the non-simultaneous sampling? \$\endgroup\$ – Ashraf Almubarak Sep 21 '17 at 12:10
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    \$\begingroup\$ I think you have a couple of options - choose a larger capacitor then drift/aging will not have the same effect or - add a dc offset to the signal to position it correctly for the ADC - if the DC offsets are small there won't be a significant error because I_DC * V_DC will be small however, it might be worth looking at the ADC spec to see what DC offsets it will erroneously generate because these may start to become significant. \$\endgroup\$ – Andy aka Sep 21 '17 at 15:12
  • \$\begingroup\$ I checked the assembly code and found that the difference between sampling time is 32 uS and correspond to 0.576 degree phase shift. The new circuit (which use larger capacitors) have a phase shift of 0.120 degree and the old one 1.8 degree. So, I must have at least a phase shift of 0.576 to compensate for the non-simultaneous sampling. Any phase more than that could be fixed by the software delays. The challenge is to have a constant phase greater than 0.56 and don't affected by the capacitor aging and tolerance. Thank you for your precious answer \$\endgroup\$ – Ashraf Almubarak Sep 21 '17 at 17:58

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