I have a circuit in LTSPICE which is performing as desired but I could not understand the working of it. Basically I have an NMOS circuit shown below (fig a):
Here are some values which I calculated previously for this specific transistor: (By DC sweep of Vgs at Saturation condition(Uds>Ugs-Ut)):
- When Vgs=0.8V, Id=63uA
- When Vgs=1V, Id=104uA
- When Vgs=1.2V,Id=151uA
Now, If I wanted to do current biasing, I set the current (current biasing) and get the corresponding Ugs in the same Transistor and then would distribute this Ugs to a nearby transistor for biasing (voltage biasing). I am not sure if this links with the concept of current Mirrors.
The concept which I am not able to understand is "How does the Transistor develop the Ugs with given current?" More specifically, in the given schematic, How does the Vgs(=0.8V) gets developed automatically with the given current of 63 uA) - This seems obvious if I link the calculated value at 0.8V to be 63 uA but I am not able to understand how this voltage is getting developed by MOSFET.
Is it like, when we are sending a specific current to the transistor, the transistor then sets up a resistance (Equal to Vgs/Id) and creates this voltage at Gate?
In the above circuit, Vgd=0. So, as per this post, Why MOSFET Pinchoff occurs, even though the channel is not formed at the Gate-Drain point, there is no restriction on current flow. So, is the voltage getting developed due to the shape of the channel (More at Source and less at Drain)?
Now, the KVL should be, Total voltage, Vt=Vgd+vgs. Since Vgd=0, Vgs=Vt-(threshold voltage)?. So, in the whole, I see that the MOSFET is acting like a resistor (whose value changes as per the current driven) or like a medium which allows current in a specific manner (slope in the p-substrate in the fig(b)) that creates a Gate-source potential with the given Id.
Is the above analysis correct? or Am I missing something? (And to the curiosity, why the source current has a negative direction?)