I am using the Atmel SAMA5D2 SPI interface configured as slave to communicate with an external device that insists on being master. I'm uncertain of the role of the NSS signal in this case.

In a previous project with the same SAMA5D2 but a different external device, I was keeping NSS low for 32 clocks, and then high for 4, to transfer 32 bits of data. This was working fine. However, it doesn't work with the current external device, because that one is keeping NSS low all the time it is transferring data. I only receive garbled data, which makes me suspect that data is not taken from the shift register properly. This then makes me conclude that the SAMA5D2 takes data from the shift register on the rising edge of NSS, but I cannot find any documentation to support this.

There's only one page in the datasheet (section 46.7.4 on page 1703), where it says:

If NSS rises between two characters, it must be kept high for two MCK clock periods or more and the next SPCK capture edge must not occur less than four MCK periods after NSS rise.

This implies that I was doing it correct before (NSS low for 32 bits and then high for 4 bits), but the "If" implies that it is not a requirement.

What does the SAMA5 expect from NSS in slave mode? Is there any documentation for this case?


migrated from engineering.stackexchange.com Sep 21 '17 at 11:40

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  • \$\begingroup\$ This is a better fit for the Electronics site. As it hasn't received any answers here on Engineering, I'm migrating your question in the hopes of it picking up more attention there. \$\endgroup\$ – user22021 Sep 21 '17 at 11:40
  • \$\begingroup\$ Do you have any control over the SPI master? Can you bit-bang the CS line somehow? When you say "garbled" does that mean it is garbage data that never existed in the data from the SPI master, or can you confirm that it's valid but just randomly misaligned/shifted? Also, I think this is an updated link to your datasheet. I could have found the wrong part number though. \$\endgroup\$ – ahogen Jan 27 '18 at 6:38

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