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I am reading Structured Computer Organization, 6th edition by by Andrew S. Tanenbaum and Todd Austin. Chapter 3.3.5 talks about memory chips. I'm confused about the following paragraph, which relates to the diagram on slide 17 here: http://www.iro.umontreal.ca/~boyer/IFT1227/H09/chap3-1x2.pdf

Years ago, the largest memory chips were often organized like Fig. 3-30(b). As memory words have grown from 8 bits to 32 bits and beyond, 1-bit-wide chips began to be inconvenient. To build a memory with a 32-bit word from 4096K × 1 chips requires 32 chips in parallel. These 32 chips have a total capacity of at least 16 MB, whereas using 512K × 8 chips requires only four chips in parallel and al- lows memories as small as 2 MB. To avoid having 32 chips for memory, most chip manufacturers now have chip families with 4-, 8-, and 16-bit widths. And the situation with 64-bit words is even worse, of course.

My thinking is that memory is just one giant array of bytes, and loading a 32-bit integer just grabs 4 "adjacent" bytes. But if the memory is comprised of chips that each have 8 data lines such as in (a), does it actually read a byte at the same offset within each chip from 4 separate chips at once, and then merge the result?

Also, the book doesn't explicitly say what kind of advantage chip (b) has with its single data line, but my guess is that all of the memory can be reachable (though at less bandwidth overall?) using fewer data lines in total. A 16MiB memory of 32 (512K x 8) chips would have 256 data lines, for a density of 65KiB/dataline. A 16MiB memory using 32 (4096K x 1) chips would be able to load a 32-bit word, but with only 32 data lines at 524KiB/dataline. Is this a possible advantage for chip (b), and is my work correct?

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    \$\begingroup\$ All of the above are possible - the individual components pieces implementing a memory do not need to match either the width or length of the whole. There doesn't really seem to be a singular specific question here. \$\endgroup\$ – Chris Stratton Sep 22 '17 at 18:47
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    \$\begingroup\$ Single data line is a thing when computer designs uses all different byte and word sizes for all different reasons, like 6/7/8/9 bit bytes and 6/7/8/9/12/16/18/24/32/36/40/48/56/72 bit words, then disappeared after people realize non 8-bit bytes an non-32 bit word is a PIA to use. Generally memory timing is fixed so more data lines meas more bandwidth, but more expensive. So on mobile phones you usually see 16-64 bit width but on computers you usually see 64-256 bit width. \$\endgroup\$ – user3528438 Sep 22 '17 at 18:59
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Does it actually read a byte at the same offset within each chip from 4 separate chips at once, and then merge the result?

Merge is the wrong term. A 32 bit system has a data bus that contains 32 wires. Each x8 chip feeds it's own set of eight from least significant byte to most significant byte.

For memory it's more about area than width or depth.

If you want a 32 bit system, and can find a single 32 bit wide memory chip with enough "depth" to supply your application you may get away with a single device.

If your system has an address space of 1 meg and you can get 1meg by 8 bit devices then four of those is less parts than 32 1meg by 1bits.

For similarly speed rated devices, it really all boils down to cost and real-estate.

Addition:

Interestingly one of the major factors when designing a memory chip isn't so much how much memory you can get on the wafer but how big the footprint of the device needs to be to have enough pins to access all those data and address lines.

In the old days when DIPs were king that meant large memory devices were aircraft carriers..

enter image description here

The above is a simple 64K by 8 device. Note the size of the wafer vs the device size. Most of the chip simply routed the pins to the wafer.

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