I am reading Structured Computer Organization, 6th edition by by Andrew S. Tanenbaum and Todd Austin. Chapter 3.3.5 talks about memory chips. I'm confused about the following paragraph, which relates to the diagram on slide 17 here: http://www.iro.umontreal.ca/~boyer/IFT1227/H09/chap3-1x2.pdf
Years ago, the largest memory chips were often organized like Fig. 3-30(b). As memory words have grown from 8 bits to 32 bits and beyond, 1-bit-wide chips began to be inconvenient. To build a memory with a 32-bit word from 4096K × 1 chips requires 32 chips in parallel. These 32 chips have a total capacity of at least 16 MB, whereas using 512K × 8 chips requires only four chips in parallel and al- lows memories as small as 2 MB. To avoid having 32 chips for memory, most chip manufacturers now have chip families with 4-, 8-, and 16-bit widths. And the situation with 64-bit words is even worse, of course.
My thinking is that memory is just one giant array of bytes, and loading a 32-bit integer just grabs 4 "adjacent" bytes. But if the memory is comprised of chips that each have 8 data lines such as in (a), does it actually read a byte at the same offset within each chip from 4 separate chips at once, and then merge the result?
Also, the book doesn't explicitly say what kind of advantage chip (b) has with its single data line, but my guess is that all of the memory can be reachable (though at less bandwidth overall?) using fewer data lines in total. A 16MiB memory of 32 (512K x 8) chips would have 256 data lines, for a density of 65KiB/dataline. A 16MiB memory using 32 (4096K x 1) chips would be able to load a 32-bit word, but with only 32 data lines at 524KiB/dataline. Is this a possible advantage for chip (b), and is my work correct?