2
\$\begingroup\$

The datasheet says the PGOOD signal is open drain but I want to use a 3.3V microcontroller to read PGOOD

  1. with the internal pulldown resistor, when PGOOD is asserted - will the voltage at the pin be 12V (my input voltage to the TPS56221)?

  2. The example design in the datasheet has PGD tied to BP through a 100k resistor - why do they do this?

  3. For my case using the 3.3V logic level microcontroller should I untie PGOOD from BP and use a voltage divider to get 3.3V ?

Thanks in advance!

\$\endgroup\$
6
\$\begingroup\$

For your application connect the PGOOD output to a pullup resistor to your 3.3V supply and tie the signal also to the input of your MCU.

If you do not have an available 3.3V connection for the PGOOD pullup you can indeed use a combination pullup to the TPS56221 BP supply and a pulldown to GND to limit the upper voltage level of the PGOOD signal. Use the formulas for a voltage divider (considering that the PGOOD signal is not pulling to GND) to compute the appropriate resistor values. Make sure you do not use too low of resistor values so that you do not put excessive load on the BP supply pin.

An open drain output from the TPS56221 means that the device can only pull the PGOOD signal to ground (which it will do whenever the output voltage is not within an acceptable range). It relies upon an external pullup resistor to some voltage level to produce the high level of the signal when the output voltage comes into range. The reason that open drain signals are used in this instance is specifically so that the PGOOD can be adapted to the logic levels of whatever control/monitoring system is in use whether that be powered from 1.8V, 2.5V, 3.3V or even 5V.

\$\endgroup\$
  • \$\begingroup\$ Ah I see, I thought open drain was pulled to the TPS56221 VCC hence the specification of the 30 Ohms (in hindsight this is really small for a pull-up/pull-down resistor) in the Electrical Characteristics. Do you know what this pull-down for ? \$\endgroup\$ – VanGo Sep 24 '17 at 11:43
  • \$\begingroup\$ @VanGo - The 30 to 70 ohm pulldown on the PGOOD signal is described in section 7.3.9 of the datasheet that you linked. As soon as the power to the device gets present the open drain FET can get proper gate drive from internal to the device. \$\endgroup\$ – Michael Karas Sep 24 '17 at 11:52
  • \$\begingroup\$ I thought that was the 750k resistor (connects drain to gate) shown in the block diagram in section 7.2? Or is 30 Ohm resistor just not shown? \$\endgroup\$ – VanGo Sep 24 '17 at 15:18
  • \$\begingroup\$ @VanGo - It is the 750K resistor!! When the chip is powered down that resistor will sink some current into the gate allowing the open drain NFET to turn on to a level of 30 to 70 ohms from drain to source. They do qualify that when the NFET is biased this way that the drain to source voltage can only go down to about a diode drop (0.65 to maybe 0.8V). This ON level of the NFET is a steady state resulting from the threshold voltage of the NFET. If it tries to turn on harder to reduce the voltage it reduces the gate voltage leading to turning it back off some. \$\endgroup\$ – Michael Karas Sep 24 '17 at 15:31
  • \$\begingroup\$ Did you mean to say "open drain" where you have "open collector"? (at the beginning of the 3rd para) \$\endgroup\$ – zwol Sep 24 '17 at 19:14

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.