1
\$\begingroup\$

I am trying to synthesize a combinational logic block in verilog using Xilinx Vivado. I am trying to reduce the number of luts and still try to find the critical path of the circuit.

Many solutions tell that the timing analysis is done from register to register. However if the output are made as registers the area of my design increases.

Is there a way to find the critical path of the behavioural design without using output registers?

\$\endgroup\$
1
\$\begingroup\$

How to constrain the paths without registers?

Yes, there is a way. Timing paths don't have to be from register to register. A port also can be a startpoint or endpoint. If your block is completely combinational, all paths will be from input ports to output ports.

The most important thing here is to define a virtual clock and input/output delays in an XDC file. Then you must add the file to the Vivado project.

create_clock -name VCLK -period 10.0 -waveform {0 5.0}

set_input_delay  1.0 -clock [get_clocks VCLK] [get_ports IN1]
set_output_delay 2.0 -clock [get_clocks VCLK] [get_ports OUT1]

The example above tells that IN1 signal arrives to the block 1ns after VCLK rises. In addition, OUT1 has to be set 2ns before VCLK rises. Since our clock period is 10ns, the path from IN1 to OUT1 has 7ns (10-1-2) to finish the operation.

How to see the critical path in Vivado?

Once the implementation is completed, click "Reports" at the bottom of Vivado GUI. Then click "Timing Summary Report" under "Route Design". As an alternative, you may also search blabla_timing_summary_routed.rpt file in the project directory.

This report shows the critical paths for all clock domains. Since you have only one clock domain, you should see something like below.

From Clock:  VCLK
  To Clock:  VCLK

Then find the section "Max Delay Paths". You will see the critical path below it.

\$\endgroup\$
  • \$\begingroup\$ This approach will allow me to check if the design runs for a predetermined amount of time, but won't give me a critical path delay time ( which is what I am looking for). \$\endgroup\$ – Aditya Pradeep Sep 25 '17 at 14:35
  • \$\begingroup\$ @AdityaPradeep I added the information to see the critical path. \$\endgroup\$ – ahmedus Sep 25 '17 at 15:08
  • \$\begingroup\$ Thank you ,this method works. However, what I meant to ask in my previous comment was about the critical path time. (From what I understood this method allows me to check if the design works for a given frequency. I need to find the maximum frequency for which the design still works.) \$\endgroup\$ – Aditya Pradeep Sep 26 '17 at 10:58
  • \$\begingroup\$ @AdityaPradeep Xilinx ISE was giving an estimation value for max frequency, however the estimation was not much accurate. I don't know if Vivado also does this. You can define a tight clock period and then subtract the slack from it after synthesis. This method has moderate accuracy to my experience. The most accurate way is to run synthesis iteratively. If you have only one block, I think you can do it even manually. \$\endgroup\$ – ahmedus Sep 26 '17 at 11:11
0
\$\begingroup\$

I am not using Xilinx, but the commands look familiar with a tool I used in the past.

With some luck the script "reportCriticalPaths" on page 25 in Vivado Scripting Documentation is of help. It is basically using the output from "get_timing_paths -delay_type $delayType -max_paths 50 -nworst 1" to list the paths in a CSV file.

To get critical paths, you probably need constraints on your paths. IMHO you can use "set_max_delay" to do so. Set the max delay to a small number from your combinational inputs to the combinational outputs (for timing analysis) and you'll probably get the worst paths reported as violators. As far as I remember that is the kind of trick that I applied for this stuff.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.