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Someone please explain to me how the circuit below operates as NOR gate. I have created a truth table next the diagram based on my understanding of basic MOSFET switching. For the output to be equal to Vdd, transistors Q1 and Q2 should be conducting while Q3 and Q4 must be non-conducting. It appears to me that the output can never be HIGH.

enter image description here

IN A | IN B | Q1 | Q2 | Q3 | Q4 | OUT

---0-----0----ON--ON--OFF--ON-----0

---0-----1----ON--OFF-OFF--OFF----0 (floating?)

---1-----0----OFF-ON--ON---ON-----0

---1-----1----OFF-OFF-ON---OFF----0

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  • \$\begingroup\$ In your first line of the truth table why would Q3 and Q4 be in different states with the same inputs? \$\endgroup\$ – Transistor Sep 25 '17 at 10:48
  • \$\begingroup\$ Q3 (N-channel) connected to LOW A must be non-conducting. Q4 (P-channel) connected to LOW B must be conducting, if I'm not terribly mistaken. \$\endgroup\$ – DorkOrc Sep 25 '17 at 10:50
  • \$\begingroup\$ Sorry, I missed the arrow direction. Where did you get the diagram? Link? \$\endgroup\$ – Transistor Sep 25 '17 at 10:53
  • \$\begingroup\$ It's from a paid review platform. I think they got it somewhere else tho because I checked with google and confirmed it's indeed a NOR gate \$\endgroup\$ – DorkOrc Sep 25 '17 at 10:54
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    \$\begingroup\$ Just noticed the arrow directions. It's a mistake in the diagram; Q4 should be an N-channel MOS. \$\endgroup\$ – nav Sep 25 '17 at 11:01
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Pay attention to the transistor polarities, and draw them correctly. It looks like Q1 and Q2 should be P channel, and Q3 and Q4 N channel. You've got them drawn every which way, and even inconsistent with themselves.

Details matter in engineering. Once you correctly show the transistor polarities, the operation of the circuit should become obvious.

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Q1 and Q2 are P-channel mosfets - they conduct when their inputs go LOW, while the N-channel mosfets - Q3 and Q4 conduct when their inputs are tied HIGH.

So When INA is LOW: Q1 is ON and Q3 is off

When INB is low: Q2 is ON and Q4 is off

When both are tied low, it leaves us with both Q1 and Q2 creating a path from Output to VDD while Q3 and Q4 floating which completely disconnects Output from Ground. In other words, Output is HIGH when INA == INB == LOW.

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