2
\$\begingroup\$

I have designed a comparator with hysteresis and rail to rail operation and my output depicted in figure1.The inputs of the comparator is a sine wave signal and a triangular waveform as shown below.Vdd is 1.2V and the transistor technology is 65nm.I am little confused about the reason for the small undesirable fluctuations as shown with the red arrow in figure 1. Which is the reason of these fluctuations? How I can improve my output PWM signal to look like the figure2.

Also in figure 3,4,5 depicted the comparator circuit with the hysteresis. The input of the left transistor is the sine waveform which shown in figure 1.It's the output of the rail to rail circuit as shown in figure 6. DC analysis is shown in figure8,9,10,11,12.

Furthermore in figure 7 depicted the output sine waveform of the rail to rail circuit with small also fluctuations when I connect the rail to rail amplifier with the hysteresis circuit. Why its appear?

Thanks in advance!

figure 1

enter image description here

figure 2

enter image description here

figure 3

enter image description here

figure 4

enter image description here

figure 5

enter image description here

figure 6

enter image description here

figure 7

enter image description here

figure 8

enter image description here

figure 9

enter image description here

figure 10

enter image description here

figure 11

enter image description here

figure 12

enter image description here

\$\endgroup\$
  • 2
    \$\begingroup\$ It's pretty obvious the fluctuation is in synch with the saw-tooth wave. Probably something is dropping the rail when it switches from down to up. You likely need more rail capacitance and decoupling too. But without a schematic how is anyone supposed to tell you. \$\endgroup\$ – Trevor_G Sep 26 '17 at 21:34
  • 2
    \$\begingroup\$ Can you post also the circuit diagram (with part number of components used?) \$\endgroup\$ – next-hack Sep 26 '17 at 21:34
  • 2
    \$\begingroup\$ What opamp are you using? It looks to me as though it isn't anywhere near fast enough - the edges of your output are nasty and slow. Might be because it's taking a while to come out of saturation. \$\endgroup\$ – brhans Sep 26 '17 at 21:45
  • 1
    \$\begingroup\$ I'm confused you have R2R input amp buffering a sine wave, then feeding an nmos input comparator? 0V is not in the cmr of the comparator \$\endgroup\$ – sstobbe Sep 27 '17 at 0:01
  • 1
    \$\begingroup\$ Ok - so you're building it from scratch and not using an opamp. But my initial diagnosis remains - it's just too slow coming out of saturation. Those edges are terrible. \$\endgroup\$ – brhans Sep 27 '17 at 1:13
1
\$\begingroup\$

You have hit the phase-reversal problem. Your lower rail input is limited because of the current source there. There are many techniques to fix that. The easiest is to limit the input voltage such that you do not close to the rail that is sensitive. For this you might need to switch your N-FET diff pair into an P-FET diff pair, if you have to work close to GND. Another way is to design a rail to rail input stage.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.