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Sorry if my the answers to my question is just "look up the specs of CMOS", I wasn't able to find it, only data on the manufactoring process.

Doing research on a project, being new, I found a forum thread about someone wondering about some CMOS specifications. The numerous answers on this thread feel conflicting to me, excluded the "never leave unconnected wires" rule of thumb.

My questions then are : Are external resistances required for input/outputs/Vcc pins, or are there internal resistances ? If internal resistances are used, how much current are the chips designed for ? Does it depend on the chip itself ? Then what specification should I look for ? Why are there max current on output pins and not min currents too, if the internal resistances are huge (0, and x amps) ?

Sorry if it feels I just need a complete guide on CMOS technology, I wasn't able to find a good one, and sorry too if my questions are simply dumb.

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  • \$\begingroup\$ There is always an internal resistance - it will just be very, very high by almost any standard. If you are talking about pull-up and pull-down: this depends on the architecture of the output/input and the application. Some (I believe most of the ATTINY family) have internal pullup resistors that can be enabled by code \$\endgroup\$
    – Joren Vaes
    Commented Sep 28, 2017 at 19:57
  • \$\begingroup\$ I just need a complete guide on CMOS technology have a look here: nutsvolts.com/magazine/article/… that seems to cover most of the basics. \$\endgroup\$ Commented Sep 28, 2017 at 20:23

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Are external resistances required for input/outputs/Vcc pins, or are there internal resistances?

schematic

simulate this circuit – Schematic created using CircuitLab

Figure 1. Various CMOS input configurations.

  • (a) If the input voltages stay within the power rails - \$ 0 \leq V_{IN} \leq V_{CC} \$ then no series resistance is required.
  • (b) If the input voltages can go outside the power rails then a series resistor on the input is required to limit the current through the parasitic input protection diodes.
  • (c) and (d) If the input can be disconnected then a pull-up or pull-down resistor should be used to pull the input to \$ GND \$ or \$ V_{CC} \$. See "Floating Inputs" below for more.

Adding resistance to the \$ V_{CC} \$ pin would be most unusual and never done in standard circuits.

If internal resistances are used, how much current are the chips designed for?

Internal resistances generally are not used. The input resistance is that of the insulated FET gates and this is > 10 MΩ.

Does it depend on the chip itself?

It depends on the logic family as each family will use a standard building block for an input.

Then what specification should I look for? Why are there max current on output pins and not min currents too, if the internal resistances are huge?

schematic

simulate this circuit

Figure 2. A simple CMOS inverter. When the input goes high M1 turns off and M2 turns on pulling the output low. When the input goes low M1 turns on and M2 turns off pulling the output high. Note that the parasitic input protection diodes are not shown.

The input impedance (resistance, if you like) is very high. This is indicated in the FET symbol by the gap between the gate and the conduction path: there is no direct current path.

The output impedance is much lower. Again, we can see that the only resistance on the output is that of M1 or M2's fully on resistance. This low output impedance is a characteristic of most amplifiers. A small input signal drives a stronger output signal. This is a requirement for "fan-out" too so that one output can drive the inputs of multiple other gates.

To answer your question, the maximum output current is limited by the current carrying capacity of M1 and M2 transistors. There is no minimum current. The outputs can be left open-circuit.

Floating inputs

CMOS inputs should never be left floating. This is because the input impedance is so high that the input could float to an undefined level between 0 and \$ V_{CC} \$ and the logic state would be undefined. With reference to Fig. 2 again, the danger is that at some input voltage both M1 and M2 will be turned partially on simultaneously. This could result in passing a significant current through the chip via M1 and M2 causing heating, waste of power and possible destruction. The solution is to pull up or down as shown in Figs. 1c and 1d.

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  • \$\begingroup\$ Very complete, detailed, and friendly answer, thanks a lot. \$\endgroup\$ Commented Sep 28, 2017 at 20:58
  • \$\begingroup\$ You might have missed the update completed just as you accepted. Thank you. \$\endgroup\$
    – Transistor
    Commented Sep 28, 2017 at 20:58
  • \$\begingroup\$ If the current at the CMOS pin (that it is input or output) is sourced in configuration (a) (i.e by another chip getting a logical 0 as output) What typical current can the diodes support before malfunctionning ? Most of the chips I'm looking at are 20 mA, but I would want this to be as general as possible. \$\endgroup\$ Commented Sep 28, 2017 at 22:00
  • \$\begingroup\$ If the input of Figure 1a is logic 0 then D1 is reverse biased and will not conduct so I = 0. D2 will have both anode and cathode at ground, there will be no voltage difference across it so its current will be zero as well. Most datasheets just say don't go below -0.3 V and don't go above \$ V_{CC} + 0.3 \ \mathrm V \$. If you need to handle more than 0.5 mA I wouldn't rely on the internal diodes. That's not what they're for. \$\endgroup\$
    – Transistor
    Commented Sep 28, 2017 at 22:16
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1) Do not put a series resistor on unless you know why you need it (almost never in normal CMOS)

2) Some devices have internal pull-up resistors. They're usually fairly large (10k - 100k). Standalone logic chips usually don't have them.

3) Outputs can be left unconnected and have a minimum current of zero.

4) Do not forget the decoupling capacitor, connected between vcc and gnd as close as possible to the chip.

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Most ICs are designed to operate from a fixed power supply, and should not have any resistor between the power supply and their power input pin.

CMOS inputs are very high impedance, and if left unconnected will float randomly between Ground and Vcc. Whether pull-up or pull-down resistors are required will depend on the application. If fed from logic chips with "totem-pole" outputs (outputs can both pull up and pull down) no resistors will be required. If the input comes from a switch or an IC with "open collector" outputs, a pull-up or pull-down resistor will be required to pull the input to the inactive state.

If an IC has an open-collector output (it can only pull the output pin to ground), then a pull-up resistor will be required somewhere to make the output high when the IC is not pulling it low.

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CMOS families follow the same rules withing each family and ESD protection to each rail is consistent for all.

Generally the higher voltage families are also higher RdsOn driver impedance meaning incremental voltage drop for rising current. The original CMOS 4xxx family up to 18V was about 150 Ohms and rose to 350 ohms or so down at 5V. Then 74HCxxx logic at 5V started at 50~75 Ohms and rises at 3.3V. Then 3.3V logic starts at 25 Ohms and rises at lower voltage. The datasheet Vol/Iol indicates this for a specified Vcc and temp. (nom / max)

Capacitive loads affect the rise times. When the propagation delay approaches the rise time then reflections from mismatched impedances at the inputs becomes essential, but for shorter propagation delays, capacitance merely affects rise time.

When the rise times are fast, the mismatched load impedance tends to cause overshoot which can be clamped by the ESD diodes if excessive, but a better practice is to try to use trace width and gaps to gnd plane that match which gives a low impedance in the 50 ohm range. Calculators for microstrip and stripline assist in trace design, when this becomes more critical at higher clock speeds with 74ALCxxx family such as ARM devices and glue logic.

There is much more to this, but at least this gives you a hint of how MOBO's and modern CMOS logic is designed. Each CMOS gate like FETs has a nonlinear C where the charge transfer for Q occurs at the switching threshold. This in turn causes a current spike and is the reason for dynamic power dissipation. (f vs Pd)

Pullup/downs may be ganged to a shared 10k (not critical) resistor for testing purposes for unused inputs.

Design for Testability (DFT) is an important aspect as well as EMC (compatability) and power and signal integrity.

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