# Why do TTL pulse generators generate an asymmetrical square wave (unlike CMOS)?

I've read that the asymmetrical (about 1/3 mark-to-space) output waveform is due to input gate characteristics of a TTL inverter, but I want to know more about which characteristics of the TTL input gate causes this asymmetry. Thanks!

• For one, the switching threshold for TTL is about 0.8 V while for CMOS it is Vdd/2. – The Photon Sep 29 '17 at 16:03
• ... and the TTL inputs source some significant current. – Transistor Sep 29 '17 at 16:22

Two reasons. First, a TTL input is actually an output. It sources a current that must be shunted to ground to be seen as a logic 0. This current affects the charging rate of the timing capacitor, adding to the current from the output through the timing resistor. Above 2.4 V the input no longer sources current out the input pin. When the output goes low, the timing resistor discharges the timing capacitor, but when the capacitor voltage gets low enough the input starts sourcing current into it, changing the discharge rate.

Separate from that, as above, the two input transition levels (there are two because of hysteresis) are not centered about a voltage equal to half way in between the two extremes of the output voltage. A typical TTL high output is around 3.5 V, so a "CMOS equivalent" set of input transition levels would be centered around 1.7 V. But the two TTL transition levels are centered around 1.3 V (original 7414), so the charging and discharging currents through the timing resistor are not equal.

https://en.wikipedia.org/wiki/Transistor%E2%80%93transistor_logic

https://en.wikipedia.org/wiki/Schmitt_trigger

CMOS Schmitt triggers have the two threshold voltages at $\frac 1 3 V_{DD}$ and $\frac 2 3 V_{DD}$. Furthemore $V_{OH}=V_{DD}$ and $V_{OL}=0$.

Since this is symmetric with respect to $V_{DD}/2$, it follows that the timings $T_H$ and $T_L$ are approximately equal, from the equations:

$$V(t=T_H)=V_{t+}=\frac {2}{3}V_{DD}=V_{DD}+(\frac {V_{DD}} 3 -V_{DD})e^{-\frac {T_H} \tau}$$ $$V(t=T_L)=V_{t-}=\frac {1}{3}V_{DD}=(\frac {2} 3 V_{DD})e^{-\frac {T_L} \tau}$$

(The two equations give the same $T_L$ and $T_H$).

This of course holds true if R is much higher than the inverter's pMOSFET and nMOSFET on-state resistances, and if the thresholds are exactly as shown. Minor variations will give you a non 50% duty cycle.

TTL devices, not only have asymmetrical thresholds (0.9 V and 1.7 V), but also the no-load logic levels are approximately $V_{OH}=3.5\ V$ and $V_{OL}=0.2\ V$. The two thresholds are not "centered" in this range. Furthermore they have a very non negligible input current (especially for large values of the resistor), which changes the equivalent charging/discharging resistance seen by the capacitor.

EDIT:

If you need a 50% duty cycle with the TTL (but also on CMOS), then you can for instance use half the capacitance (the frequency doubles) and cascade a T-flip flop (the frequency what you originally wanted, and the duty cycle is 50%).

Your example circuit shows a Schmitt-trigger inverter. Look at the threshold voltages in the example table...their average is less than half-Vcc:
The capacitor charges toward Vcc (or Vdd) faster than it discharges toward ground. This voltage threshold asymmetry is a major contributor to pulse-width asymmetry.

If Schmitt thresholds were symmetrical about half-Vcc, output pulses should be close to 50% high, 50% low. I am assuming that the gates' output stage pulls high (toward Vcc) in a similar way as it pulls low (toward ground). Asymmetry in a gate's output stage is another source of asymmetry, if current is flowing into a load.

• Those do not look like TTL transitions levels. – AnalogKid Sep 29 '17 at 19:04
• @AnalogKid Certainly, the table is for HCMOS schmitt...(TTL is only spec'd for Vcc=5V). For the TTL schmitt (7414), average threshold is worse, about 1.2V, causing even worse pulse skew. And TTL output stage asymmetry causes even more pulse skew in the OP's oscillator. HCMOS is preferable, but not perfect. – glen_geek Sep 29 '17 at 22:42

The character of CMOS thresholds allows a symmetric placement of the positive and negative trip points of the Schmitt circuit, and of the logic output drive voltages relative to those trip points. So, the voltage across the feedback resistor may be 5V - 1.66V when the CMOS first goes HIGH, and 0V - 3.33V when it first goes LOW. Those equal (though opposite) voltages make equal currents and take equal times to charge that capacitor, so you get a 50% duty cycle. Charge and discharge currents are in the ratio 1:1.

In TTL, however, the thresholds may be around 1.4V (like, 1.2V low and 1.6V high), while the output drive levels are 3.2V high and 0.5V low. So, voltage drops across the feedback resistor are 3.2V-1.2V in one phase, and 0.5V-1.6V in the other. That means the currents that charge and discharge the capacitor are in the ratio of 2.1:1.1, and that is NOT how you get a 50% duty cycle.

The important character of TTL is that input thresholds are better controlled than CMOS (have a small uncertainty) and the output voltages have less symmetry than CMOS. After that, it's just figuring of details.

Do not assume you have 50% duty cycle with CMOS. Process variations: doping, implant ion beam energy, annealing temperatures and times, etc contrive to implement functioning circuit that may be far from nominal performance.