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So first, sorry if I make some incorrect assumptions or statements. If I do, just correct me and forgive my ignorance.

It seems like everything I've been taught so far in classes about transistors and CMOS circuits utilizes an idealized model to get the concepts across, but I still feel like I don't have the tools to design a circuit for myself, where certain parameters aren't provided to me beforehand. I'll try to list exactly what it is I don't understand:

  1. How do I decide the timing variables for a circuit implementation? I understand its application specific, but how do I know if I should choose components with relatively low delay or if I can afford high delays? How do I quantify my delay requirements? Maybe I start with, say, what I want my throughput to be at the circuit output, and work backwards down to the transistor level?
  2. Related to the timing thing, how do I know what scale I should use for my transistors? My assumption is its some combination of allowable space, monetary cost, and the delay tolerances needed for the application. That seems like an awful lot of things to juggle. Are there any rules for determining this?
  3. Finally, what about non-ideal effects like input capacitance? It seems like I'd I just use this as a guide to make sure that my desired clock frequency does not suffer severe attenuation from parasitic effects. Or do these non ideal effects have a much different role in choosing parameters for the circuit?

I think that each point is related enough to warrant making only one question, though I can split this into multiple questions it turns out each point requires deeper explanation than I initially thought.

Thanks in advance for any help you can provide.

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How do I decide the timing variables for a circuit implementation? I understand its application specific, but how do I know if I should choose components with relatively low delay or if I can afford high delays? How do I quantify my delay requirements? Maybe I start with, say, what I want my throughput to be at the circuit output, and work backwards down to the transistor level?

Within electrical engineering, there are many sub-disciplines. Some of these may be addressed in classes you take, some of them you just have to learn yourself through experience and/or self-teaching. The answers to these questions often come with application-specific knowledge.

For example, one of these disciplines is analog signal conditioning. Not all good EEs are well-versed in this, and some are expert analog designers who know the answers to all of your questions when working with BJTs and op-amps, but can't answer them easily when it comes to high speed digital circuits. The way you speak of delays seems to imply a digital context, but if you have too much phase shift (phase shift is a type of delay!) in the feedback loop of an amplifier (while the gain is >1), the amplifier will oscillate.

Once you get a specific type of circuit to design, there will also be literature with "working examples" available. Look at any switching power supply's data sheet for example. Here's a random datasheet to look at http://cds.linear.com/docs/en/datasheet/8711f.pdf, it has plenty of application circuits which will give you a starting point for selecting components and as well as PCB layout considerations.

Related to the timing thing, how do I know what scale I should use for my transistors? My assumption is its some combination of allowable space, monetary cost, and the delay tolerances needed for the application. That seems like an awful lot of things to juggle. Are there any rules for determining this?

Another example. Following the switching PSU theme, when selecting a MOSFET as the switch for a power supply, you typically want to use a MOSFET which is marketed specifically for this purpose, which significantly narrows your search and helps you in the quest to determine which of the tens of parameters describing the transistor are relevant to your application.

Finally, what about non-ideal effects like input capacitance? It seems like I'd I just use this as a guide to make sure that my desired clock frequency does not suffer severe attenuation from parasitic effects. Or do these non ideal effects have a much different role in choosing parameters for the circuit?

Again, this knowledge comes with experience, talking to people more experienced than you, reading datasheets, etc.

To address parasitic capacitance specifically, here are some things to consider:

  1. Parasitic capacitance slows down switching times, which can lead to unnecessary increased power usage.

  2. Whatever output pin is driving the input with the parasitic capacitance needs to be able to provide enough current to charge the capacitance quickly enough. This is why we have these things called "gate drivers". Because a little MCU GPIO pin is not equipped to handle the job of driving the large capacitance of a power transistor's gate. See What is the purpose of "MOSFET driver" IC's .

  3. Capacitances (parasitic or otherwise) can work with inductances (parasitic or otherwise) to cause your digital signal switches to "ring" or "overshoot" which is bad for signal integrity and can even damage components. This type of problem is often best looked at in terms of transmission lines and impedance matching rather than talking about capacitances and inductances.

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Welcome to the real world of EE. A lot of what we do is from experience grounded on the solid theoretical teachings.

As you suspect in your first point, job number one is to nail down EXACTLY what you want your circuit to do including what tolerances you can accept. Having that knowledge in hand gives you a chance to select appropriate technologies and design your circuits to potentially conform to your specification.

Whenever possible use simulation tools to verify that the circuits do indeed do what you expect and ultimately build prototypes and verify it in reality. When necessary change or improve your design as appropriate.

When it comes to selecting particular parts it can indeed be a lot of balls to juggle. Sometimes it is easy, there may only be one part that does the job, other times the choices are so wide you need to find one that functionally works to your requirement and is acceptable in cost etc. and just go with it.

As for the more extreme characteristics. The thing here is to recognize when you are heading into dragon territory. Then spend the extra time on those areas, and or get help from a more experienced designer.

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    \$\begingroup\$ +1 for "other times the choices are so wide you need to find one that functionally works to your requirement and is acceptable in cost etc. and just go with it." It's easy to get stuck in a rut overthinking something, learning to go with the "good enough" where optimization is not required is an important skill. \$\endgroup\$ – Dmitri Sep 29 '17 at 18:58
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    \$\begingroup\$ Everything in engineering is about (1) identifying unknowns and pulling them up front, to be resolved and turned into added conditions and boundaries; and, (2) resolving a complex problem that is both boundary-valued and initial-valued, as well as human-factored/subjective, and where a lot of experience as well as creativity and imagination can be usefully applied. And you can solve all of that and still completely fail if the buttons aren't "snappy enough," too. (Whatever that might mean to market research that only gets done when you are done.) +1 \$\endgroup\$ – jonk Sep 29 '17 at 19:20
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    \$\begingroup\$ lol @Jonk.. isn't that always the way. That and the "oh we forgot to tell you" or the "Oh, that's not really what I meant" factors. \$\endgroup\$ – Trevor_G Sep 29 '17 at 19:22
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Delays are up to you to decide what is tolerable.

This can be seconds for a relaxation CMOS Schmitt trigger Oscillator to picoseconds for a high speed complementary bridge driver or current mode logic.

Logic design must avoid a race condition of simultaneous switching inputs causing a metastable or glitch condition, so worst case min/max delays matter.

Delays in complementary power drivers must avoid shoot thru shorting out the supply rails, so deadtime dealy control is critical with very low RdsOn in FETs or IGBT drivers or low Rce in BJT's.

However in each CMOS family, the gate voltage and RdsOn is controlled very carefully to limit the supply drain current during the output transition, ranging from ~300 ohms in 4xxx CMOS to ~25 Ohms in 74ALCxxx series for driver impedance. Again the N and Pch devices are designed to be matched and more symmetrical outputs.

The output impedance of the drivers above can be used to estimate the rise times from capacitive loads as they are linear devices during the transition interval using RC values for asymptotic values affected by load C in cables , traces or defined loads. with pF/m values etc.

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