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This is a beginner question. I know how the logic gates with BJTs work basically to provide ON and OFF switching action. OFF state occurs when the transistor is blocked in cut-off region, and ON state occurs when the transistor conducts between the collector and the emitter.

So ON state occurs in both active region and the saturation region. I wonder in logic circuits why better to saturate to obtain ON state instead of conducting in active region? Active region seems to be avoided. Is that for stability or heating? Why?

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  1. Using the saturated state means the output voltage doesn't depend on small variations of the input voltage.

  2. Using the saturation region (or triode region for MOSFETs) can result in very low power consumption when the gate is kept stable in the 1 or 0 state.

  3. However, there are logic families that use forward active mode for the output transistors in both 1 and 0 states. For example, ECL (emitter-coupled logic). The benefit of this is that the logic can switch more quickly due to no having to move enough charge in and out of the base region to move between the off and saturated states. The drawback is that ECL is more power-hungry than CMOS when the switching frequency is low.

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Actually, in power switching they saturate (to reduce voltage losses), but in logic, it's better to not saturate transistors.

Saturated transistors have dramatically longer switch-off times. Therefore the art of using bipolar transistors in logic circuits is to keep them as close to saturation as you can (low Vce means good logic levels) without incurring the speed penalty of saturation - as explained here.

Traditionally the bulk of the switching work has been done with NPN transistors as low side switches, where slow switching off has been seen as delayed rising edges.(NPN transistors as high side switches are emitter followers, which don't saturate, but don't pull quite as high either).

This led to the asymmetric logic levels and drive strengths seen in traditional TTL, where (from a 5V supply) logic '0' is guaranteed to be below 0.8V (but typically Vce might be below 0.4V) and logic '1' is guaranteed to be above 2.4V.

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  • \$\begingroup\$ Very interesting. Two questions regarding what you wrote: 1) When you say "longer switch-off times", should we think of it like it causes a longer fall-time of a falling edge? 2) Do you mean better keeping close to 0.2V? "low Vce means good logic levels"; so can you say roughly what usually is Vce during ON state in a BJT logic? \$\endgroup\$ – Genzo Oct 1 '17 at 12:28

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