# Linear regulator loop dynamics

Given a step change in the input voltage of a standard op-amp based linear regulator, a finite amount of time is needed for the op-amp to sense the voltage difference at its input and do whatever it needs to do to make its differential input voltage nearly zero.

I'd like to know how the feedback loop is able to stabilize the output voltage when the input does not change in a step-wise fashion but is instead constantly changing with time. If the op-amp must respond to changes in the input, and this response takes non-zero time, then wouldn't the op-amp be 'chasing its tail' when the input is varying? In other words, how does the op-amp 'keep up' with the input if the input is the cause and the loop adjustment is the effect? Isn't the output adjustment always one step behind the change in the input? Is there an input frequency or dVin/dt at which the op-amp would not be able to stabilize the output frequency?

• Yes, the output "adjustment" is always "one step behind". But what you are missing is that "the one step" makes a very big difference depending whether the output load varies slowly, or fast. For "slow" changes one little step behind makes no difference, while for fast changes in load the response delay might turn the original negative feedback into positive, so the regulator will start oscillating. That's where the concept of "phase shift" comes in. For the role of gain at each frequency see Andy's answer. Commented Oct 1, 2017 at 18:43

Isn't the output adjustment always one step behind the change in the input? Is there an input frequency or dVin/dt at which the op-amp would not be able to stabilize the output frequency?

Yes it is and it boils down to a criteria called phase margin - this is a measure of the op-amps stability across the range of frequencies it is useful for.

Taken to extremes, the op-amp could be slow enough so that any counter measure taken by it to cancel an unwanted alteration in the output might actually produce positive feedback. This is how an oscillator works and most of us have heard of output instabilities in op-amps now and then.

So phase margin is the key to stability. If you look at the op-amp open-loop response below you might see what I mean: -

You can see that for low to mid frequencies the open-loop phase shift on the output is about 90 degrees - this is typical of most op-amps ran with open-loop gain and, of course, when you close the loop, the phase shift is 180 degrees. However, that isn't the case open- loop because an open-loop op-amp is like an integrator.

However, as frequency rises from the low/mid range, the "delay" factor starts to get involved and this is the same as shifting the phase. There is a point reached where the open-loop phase shift would naturally stray from 90 degrees and reach 0 degrees AND, if the op-amp is still capable of producing a gain greater than unity then there is a potential problem when the loop is closed.

Let's, for the sake of argument say that the open-loop gain were ten at a phase shift of zero degrees and, let's also say we wanted the closed-loop op-amp to have unity gain. So now, if we analyze the op-amp (open loop) AND the feedback network, the net gain back to the input (at the frequency that causes zero degrees phase shift) is over ten and bingo, the circuit oscillates.

In the picture above, we have a decent op-amp that can be run with a closed-loop gain of unity (worst case consideration) because the phase margin is approximately 45 degrees i.e. the phase shift is 45 degrees away from it becoming an oscillator when the gain falls to unity.

However, like any control loop, the down side to being able to remain stable is that fast output fluctuations (whether power supply induced or load induced or demand induced) cannot be sufficiently dealt with as they can when the fluctuations are a lower frequency i.e. the control-loop runs out of steam so to speak.

Here's the relevant performance curve from a randomly selected regulator (TI TLV760):

You can see that the ability to maintain regulation does degrade as faster changes are applied to the input. And that the exact performance depends on the output capacitor selection.

Is there an input frequency or dVin/dt at which the op-amp would not be able to stabilize the output frequency?

If your upstream source is connected to the regulator with non-zero resistance and inductance, and you use an input capacitor in the regulator circuit as is universally recommended, then these elements will prevent excessively high frequencies from reaching the regulator input.

So the regulator itself may not be able to prevent high frequency signals from being transferred from input to output, but reasonable design of the network feeding the regulator can prevent it. If you have a very high frequency interference source injecting a signal on the input, you may need more than just the basic bulk capacitor that is usually recommended.

The PSRR is a combination of active bandwidth error correction and passive slew rate limiting on the input source impedance and inductance as well as output loading.

Every LDO is different and step up and down may have the same Fourier components, but beware that the internal amplifiers are bias to source current and not sink them on the outputs, so what you see in the curves below does not tell the whole story.

There will be sufficient loop gain and phase margin to attenuate small ripple at any of these frequencies, but a large step in each direction may have different consequences depending on the load current.

Thus using low ESR input Caps and relying on the line input inductance or source impedance also plays a role, but not defined in the LDO specifications.

It is assumed you have a solid understanding of impedance ratios for step responses to passive loads that improve the PSRR of the active correction for low gain broadband internal amplifiers referenced to some band-gap voltage like 1.25V.

Note the improvements made by adding these caps.

Remember that just as Op Amps have current limits and a much lower full swing bandwidth than small signal bandwidth, the BODE plots may be misleading for a large input step voltage or output step current.

Careful attention to the choice of capacitors recommended in each datasheet are crucial to satisfy your requirements for step response pulse noise, as well as ground and Vout inductance to the load.

For much more details on this subject, read and understand this. https://www.ti.com/lit/an/slva079/slva079.pdf

## Conclusion

Due bandwidth limitation of LDO, an external network added to the input of a linear regulator improves the inherent PSRR of the LDO, especially at high frequencies, where the low quiescent current compromises the high-frequency PSRR of the LDO and gain is reduced internally by compensation.