It is recommended that the inputs and the output of the LPM_MULT be registered. This will make it possible to achieve highest frequency for the design, although introduce latency.

With latency of 0, there is no clock input for LPM_MULT. However, adding latency of 1 adds clock signal although it does not increase the resource usage.

Therefore, in order to "register" the outputs of the LPM_MULT, do I explicitly register its output in a process that has rising_edge(clk) in it? Or do I take it for granted that the output is actually internally registered when I set clock latency to 1 although the resource usage does not change when latency is 0 or 1??


1 Answer 1


Setting the output latency to a non-zero value instructs the LPM to include output pipeline registers. Setting the latency to 1 will indeed correctly add an output register stage which will help to achieve better speed performance.

The "Resource Usage" box is really only advisory, and the actual usage will depend on implementation, device family, and optimisation settings. As such this value may not show an accurate representation.

In any case, if you design uses DSP blocks for optimisation, you will not see an increase in resource usage when adding up to 3 cycles of latency. This is because the DSP blocks internally contain register three selectable register stages - the first is at the output (latency > 0), the second on each input (latency > 1), and I believe the third is part of the accumulator internally (could be wrong).

  • \$\begingroup\$ ok, this is critical. I have created signal to register the two inputs individually and also a signal to register the output. The user manual does not say that setting latency to more than 1 shall register the inputs automatically. So, if you have a reference kindly let me know. The design contains a lot of components and then some signals to glue them together. These glue signals shall reduce if the multipliers can have internal registers just by changing the latency. \$\endgroup\$
    – quantum231
    Oct 1, 2017 at 19:04
  • \$\begingroup\$ @quantum231 how the registers are implemented will depend on the technology. If it is utilising DSP blocks, those will register the inputs for latencies > 1 because it is the only way the registers will fit into the DSP block. If logic rather than DSP blocks is being used all bets are off. \$\endgroup\$ Oct 1, 2017 at 19:15
  • \$\begingroup\$ From experience with the core on devices without DSP blocks, the calculation tends to get split into chunks with registers evenly spaced throughout to optimise speed. \$\endgroup\$ Oct 1, 2017 at 19:18
  • \$\begingroup\$ In terms of DSP blocks, if you set a latency of zero and then in your design have pipeline registers (not part of the LPM) that don't have complex enable signals, Quartus will probably optimise the design and absorb those registers into the DSP blocks. \$\endgroup\$ Oct 1, 2017 at 19:20
  • \$\begingroup\$ In any case, the RTL viewer should show you what the LPM has inferred. \$\endgroup\$ Oct 1, 2017 at 19:22

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