0
\$\begingroup\$

I am trying to build my own JTAG programmer using the Zedboard but I am stuck with hardware issues.

For the Zedboard side, I am using the Pins XADC-GIO0, XADC-GIO1, XADC-GIO2 and XADC-GIO3 as TCK, TDI, TDO and TMS. I constrained these pins as LVCMOS25 as my target board's JTAG has a VREF of 2.5V. On my Zedboard, I used the jumper setting for the Vadj at 2.5V.

When programming the target board using the Zedboard, I simply connect the 4 JTAG pins using wires from the Zedboard to the target board and pull-up TDO using a resistor to the VREF of the target board. I do not have any buffer chips or series resistors termination or and decoupling capacitors to ground for the JTAG pins. I was thinking that TCK is 1MHz and not really that high-speed for signal integrity issues to set in?

When issuing the JTAG commands to the target board, I am however unable to read back the device ID correctly, somehow, the TDO output just isn't correct.

I checked the output from the Zedboard to the target board several times and I am certain that they are issuing the correct bits to the target board. I have also checked the setup and hold times of the TCK wrt TDI and there's nothing wrong there as well. The Zedboard and the target board are powered separately with their own power adaptors but I connected some of the ground pins on both boards together to have a common ground. (another noob mistake or is this normal?) The target board's FPGA is also a Xilinx FPGA.

If this is really a case of signal integrity issues, can anyone advise how I may solve this?

Thanks in advance.

Update 20171004 1: Ok so I stumbled upon the problem but I got no idea how to fix it. Apparently the problem seems to lie with TCK. It is the same setup but I removed the pullup resistor from TDO. Now when I issue a read Device ID and probe TCK (not TDO!) using an oscilloscope, the Zedboard FPGA reports the correct Device ID. When I remove the oscilloscope probe, the Device ID is wrong again. This isn't intermittent; placing and removing the oscilloscope probe on/from the TCK pin respectively causes the TDO to be correctly and wrongly read. Any ideas how I should solve this?

The Zedboard FPGA pins are LVCMOS25 with Drive at 16ma.

Update 20171004 2: Ok I added a pull-up resistor on TCK (no pull-up resistor on TDO) and the Device ID is read correctly everytime. Still haven't successfully configured the target FPGA but I guess at least the signal integrity part seems to be tamed a little for now.

Update 20171005: Ok I finally found the problem. Turns out my TMS pin was assigned to XADC-GIO3 (Pin J15) and this pin was the issue. Every other pin H15, R15 (respectively TCK, TDI) has a Vpp of 2.5V while J15 only has ~1point-something volts. I turned this into an input pin by swapping with TDO (K15) and everything turned out fine! No need for twisted pairs or termination or pull-up resistors on any signal - TMS, TCK, TDI or TDO. I was also finally able to program the target board with my Zedboard JTAG programmer.

\$\endgroup\$
  • \$\begingroup\$ probably, how can we see your layout and signals? Did you use twisted pairs? \$\endgroup\$ – Sunnyskyguy EE75 Oct 2 '17 at 13:53
  • \$\begingroup\$ The only connection between the Zedboard and the target board are the 4 JTAG pins (with the TDO pulled up to the target board's VREF). I am just using 4 individual wires to connect the JTAG pins between the two boards. Another wire connects the two boards' ground pins together to form a common ground. Twisted pairs as in twisting the 4 wires together? \$\endgroup\$ – bFig8 Oct 2 '17 at 13:59
  • \$\begingroup\$ I am wondering if I am using the VREF from the target board correctly? \$\endgroup\$ – bFig8 Oct 2 '17 at 14:01
  • \$\begingroup\$ How long is your cable? How fast are the rise-times? \$\endgroup\$ – Tut Oct 2 '17 at 15:17
  • \$\begingroup\$ About 20cm long. I didn't measure the rise times at the target board connector side. At the Zedboard side I guess its the normal Xilinx ZC7020 IO rise times? \$\endgroup\$ – bFig8 Oct 2 '17 at 15:28
1
\$\begingroup\$

Update 20171005: Ok I finally found the problem. Turns out my TMS pin was assigned to XADC-GIO3 (Pin J15) and this pin was the issue. Every other pin H15, R15 (respectively TCK, TDI) has a Vpp of 2.5V while J15 only has ~1point-something volts. I turned this into an input pin by swapping with TDO (K15) and everything turned out fine! No need for twisted pairs or termination or pull-up resistors on any signal - TMS, TCK, TDI or TDO. I was also finally able to program the target board with my Zedboard JTAG programmer.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.