1
\$\begingroup\$

I'm trying to debug that circuit (pic. 2).

The problem is when the input signal is near 2V the output oscilogram looks like in pic. 3 (with gap). What is the nature of that gap? Looks like some of current source don't conduct some time.

How much C3 capacitor (pic. 2) value would be? In original scheme (pic. 1) it was 22pf but with that value the oscilloscope output lag too strong (i. e. output signal is not printing with pauses of different durations)

How much R5 (pic. 2) value must be?

If I'll use the cascode output as in original schema (pic. 1) how much diodes I need (2 or 4)?

enter image description here enter image description here enter image description here

| improve this question | |
\$\endgroup\$
  • 1
    \$\begingroup\$ Is that a simulation? Might be an artifact then. Look around for other places that have an anomaly at that time \$\endgroup\$ – PlasmaHH Oct 2 '17 at 15:14
  • \$\begingroup\$ Yes. That thing is under simulation and I may found that in many different places of oscillogram. I have another working amp scheme where I set equal input voltage and see ouput with up and down clipping but without that gap \$\endgroup\$ – MaxMil Oct 2 '17 at 15:17
  • \$\begingroup\$ You highlight that one of the current sources may not be conducting at the correct time, have you probed different points in the circuit to test this hypothesis? \$\endgroup\$ – loudnoises Oct 2 '17 at 15:35
  • \$\begingroup\$ Yes but the values of current in probes changes rapidly and I don't see any zero current moments. \$\endgroup\$ – MaxMil Oct 2 '17 at 15:40
  • \$\begingroup\$ Can you overlay the probes on the scope so that you see exactly what is happening at the moment of your discontinuity? \$\endgroup\$ – loudnoises Oct 2 '17 at 17:32
1
\$\begingroup\$

This is normal behavior that closely models real life behavior. What you see here is a result of overloading and forcing some transistors from active region into saturation. In this particular amplifier topology here what happens under positive overload:
1. Q1 goes off, Q12 gets saturated, because there is no more current flowing in it from Q1
2. Q6 is off, Q10 is off, Q11 is off
3. Current source Q4, Q5 is not loaded any more, Q5 saturates.

It takes some time to bring Q2 and Q5 from saturation to active region.

C3 is there to stop oscillations. Simulation lagging typically indicates oscillation, but it has to do with your software and transistor models. Try increasing it or playing with simulation parameters.

R5 being 10k is a good guesstimate. It is there to bias Q4.

Two diodes in top output stage, four in the bottom.

| improve this answer | |
\$\endgroup\$
  • \$\begingroup\$ Good tip. Increasing C3 to 1000 pf lowers the gap but only for load resistance 4 or 8 ohm.If I use 2 ohm load that feature may be observed again. How much R5 current to bias Q4 may be? \$\endgroup\$ – MaxMil Oct 3 '17 at 16:06
  • 1
    \$\begingroup\$ C3 is called Miller capacitor in this circuit (voltage feedback amplifier) and is meant to increase phase margin to improve amplifier stability. It is not meant to reduce the clipping artifact you are seeing. The clipping artifact has to do with amplifier topology and appears only when amplifier is overloaded. To avoid it you have to use a different topology, clip signal in a controlled manner (add a circuit to do this) or, avoid overloading altogether. \$\endgroup\$ – Jurkstas Oct 3 '17 at 19:00

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.