# Question about 4-bit binary adder on 7 segment display and subtraction

In my lab, we successfully built a 4-bit binary parallel adder and were able to display the results of some tests on the 7 segment display.

But our TA asked us to try something: subtract 1-9, and we got 7. Why is that?

• how did you do the subtraction? How are we supposed to know what's wrong if you don't explain that? Oct 2, 2017 at 20:54
• I don't think anything is wrong at all: that was that TA's point. He said we were meant to get 7 on the display (even though 1-9 doesn't equal 7), but instead of telling us why, he suggested that we think about it on our own, and I haven't figured it out. Oct 2, 2017 at 20:55
• hint: integer wrapping Oct 2, 2017 at 20:56
• was it 1 or 10h-9h=7h (hex) Oct 2, 2017 at 21:06
• Wondering how, exactly, you implemented a subtraction with an adder... Oct 2, 2017 at 21:09

So basically whenever you do 1-9 in binary that looks like

00001 (1) - 01001(9)

however since most of the subtraction is done by twos complement it is actually

00001 + 10110 => 10111

Your display will only display the bottom four bits which are 0111, which is seven.

Cheers!

• OP's system is 4-bit. Yours seems to be truncated 5-bit. Can you explain? Oct 2, 2017 at 22:16
• I think that would depend on how the adder was made and implemented, as well as how was the subtraction performed. From my labs we did "adder implementations" in some sort of HDL with fpga's tied to them that could be a case, I really don't know how you would subtract -9 in a 4 bit implementation Oct 2, 2017 at 22:19
• @Transistor if you do what he did, for 4 bits, still the system only shows 0111 which is still 7. May 19, 2019 at 15:49

in binary:

1: 0001


Subtracting 9 times 1:

0000 (-1)
1111 (-2)
1110 (-3)
1101 (-4)
1100 (-5)
1011 (-6)
1010 (-7)
1001 (-8)
1000 (-9)


I would expect 1000, which is 8.