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I've created a circuit that uses both binary and BCD counters to convert an 8-bit binary number into three BCD numbers, which then feed into BCD to 7-segment decoder chips, and finally to common-anode displays.

How it works: Upon pressing a push-button, an 8-bit binary number from a DIP switch is loaded into two 74LS191 binary counters, that are wired to count down. When both of the counters have reached their minimum (i.e. they have counted down to 0), that disables all counters.

Meanwhile, once the clock starts, I have three 74LS190 BCD counters that load all zeros, and count up daisy-chained, so that by the time the disable is activated on the counters, it will have counted up to whatever the original 8-bit number is, and latch on to that value. The outputs to these feed into individual 7447 BCD to 7-segment decoder chips, which then go to a 3-digit common-anode 7-segment display.

I'm using a 555 timer for my clock, the nominal frequency is 4.8 Hz (at the moment) which I plan to kick up to about 200 kHz once everything is working. As far as I know both of these frequencies fall way less than the max frequencies for the chips (although I was unable to find a max frequency on the 7447 data sheet).

Below is the schematic. I've simulated it in Multisim and it works perfectly. However when I build it, I find that the BCD counters have a problem once it counts from 19->20 (it goes from 19->0), and sometimes even from 9->10 (sometimes going from 9->0). It seems to me that I have a problem somewhere in my daisy-chaining of the counters, but my connections on my breadboard seem fine to me. The binary counters that count down are totally fine.

Does anybody have an idea of where my circuit may have gone wrong? I'd take a picture of my breadboard, but it's a complete rats nest which I don't plan to tidy up until I get everything working properly. Grazie mille!

binary to bcd decoding circuit schematic

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  • \$\begingroup\$ You need >0.01uF on each IC for clean Vcc to Gnd. LED's reduce the Voh margin somewhat but you may have a race condition with trailing edge of async BIN CTEN_ \$\endgroup\$ – Sunnyskyguy EE75 Oct 2 '17 at 23:12
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Almost certainly you are suffering from ground and/or decoupling issues.

Assuming you are using a solderless breadboard setup, you should do 2 things. First, find some way to beef up your ground system. Try, for instance, running ground wires vertically as well as horizontally, and use ground wires as short as possible. No big loops of wire. Second, at each IC install a 0.1 uF ceramic cap from Vcc to ground, and put each cap as close to the appropriate pins as possible. Connect each directly to the space nearest the pin. Under no circumstances should you run jumper wires from the IC to a cap placed elsewhere on the board.

This may or may not work. An even bigger issue is that you are misusing your counters. These are synchronous, not ripple. So connect all the clocks together. In each counter chain, connect RCO to CTEN of the next counter.

Finally, you need a debounce circuit on your switch. You can do this using

schematic

simulate this circuit – Schematic created using CircuitLab

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  • \$\begingroup\$ This worked perfectly! I've never made a project before that really needed decoupling caps, so I suppose I've been lucky, and that luck failed. I didn't change how I daisy-chained the counters, and they still work fine. I'm not convinced that was in error. \$\endgroup\$ – lemontwist Oct 3 '17 at 12:40
  • \$\begingroup\$ @lemontwist - The point is not that using your counters as ripple counters CAN'T work, rather that they might and they might not. I haven't done a detailed analysis of your circuit, but I suspect you got lucky. Tony Stewart is absolutely correct to have suspected a race condition, although if the circuit now works, there is obviously no problem along those lines. The thing is, this may be restricted to the specific chips you've used, details of the board layout and wire lengths, and operating temperature. Among other things. Learn how to use synchronous logic - it will make your life simpler. \$\endgroup\$ – WhatRoughBeast Oct 3 '17 at 15:14
  • \$\begingroup\$ Interesting. The data sheet says that "The counters can be easily cascaded by feeding the ripple clock output to the enable input of the succeeding counter if parallel clocking is used, or to the clock input if parallel enabling is used." I want to use parallel enabling. \$\endgroup\$ – lemontwist Oct 3 '17 at 17:37
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In addition to my comments about a race condition on CTEN_ and IC decoupling on Vcc was alway recommended for each IC, I think the problem is the following;

TTL fanout for signal integrity is 1:10 but each CEN_ has a fan-in value of 3 so with 5 counters you are exceeding the fan-out capacity of 10 by 50% for Iol,Ioh on U4A.

You can verify the trace with very short leads to a 10:1 probe and measure the voltage against TTL spec is Vol=0.8max and Voh=2.0V .

The defacto TTL input threshold is 2 diode drops. (2Vbe)

Poor man's test: If signal integrity is the problem test this with 2 resistors biased 100R pulldown or 1K pullup.

If this is all CMOS and not actually what is in your schematic, then you wasted my time.

Hope you have a bounce free switch, but I don't think that is your problem.

Last thought is that it is the ripple carry out RCO_ that faults in clocking or not to the next BIN MSB.

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  • \$\begingroup\$ Thanks. It is indeed all TTL. All of the chips are as labeled. Do I just use buffers on the inputs to each ~CTEN pin to solve the fain-in problem? (I know it sounds like a stupid question but I've never actually dealt with fan-in problems in real life.) \$\endgroup\$ – lemontwist Oct 2 '17 at 23:45
  • \$\begingroup\$ Measure the actual signal integrity and look for glitches on RCO_ \$\endgroup\$ – Sunnyskyguy EE75 Oct 2 '17 at 23:48

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