# Maximum load resistor for a given single transistor circuit

Following parameters are given for the above circuit:

R1=8.2 kΩ, R2=5.6kΩ, RE=2.7kΩ, VEB=Uj=0.7V, Vcc=10V, β=200

The question asks the maximum load resistance RL for the transistor in active mode.

I solve the question in the following way:

The maximum load resistance RL for the transistor in active mode means to me the transistor is approaching to saturation at that point.

So for that point, I take Vce=0 and set Vy=Vx+0.7V.

Since Vx=Vcc*R2/(R1+R2)

Vy=Vcc*R2/(R1+R2) + 0.7V

Vy=10*(5.6/13.8) + 0.7V = 4.76V

Now since Vce=0V, and Ie=(Vcc-Vy)/Re = 1.94mA

Ic = Ie approximately so

RL = Vy/Ic = 4.76V/1.94mA = 2.45kΩ

So I calculate the maximum RL in active region as 2.45kΩ, whereas the answer is 2.1kΩ.

Is my calculation wrong?

• Active mode =/= saturation; you will have some voltage drop from collector to emitter. – Don Joe Oct 3 '17 at 1:21
• Vce=0 means the transistor is in hard saturation. Vce> 200 mV is more realistic. Solution likely uses Vbc =0 – sstobbe Oct 3 '17 at 1:21
• I agree with @sstobbe. The answer uses $V_{BC}=0$, which is the same place I use to demark the end of the active region and the start of (very shallow) saturation. (You should get a base current of about $9.6\:\mu\textrm{A}$, which I think you do.) – jonk Oct 3 '17 at 1:24
• Vce = Vbc+Vbe vectorially. When Vbc=0 since Vbe is always around 700mV, does that mean the question takes Vce=700mV instead of zero? – user1999 Oct 3 '17 at 1:43
• Yes the point where Vce = 700 mV is a good point for separating the active mode and saturation regions. – Bimpelrekkie Oct 3 '17 at 6:42

The following two schematics are equivalent:

simulate this circuit – Schematic created using CircuitLab

Where $V_{TH}=V_{CC}\frac{R_2}{R_1+R_2}$ and $R_{TH}=\frac{R_1\cdot R_2}{R_1+R_2}$.

From the above, and assuming $I_B^{'}=\mid I_B\mid$ and $V_{BE}^{'}=\mid V_{BE}\mid$, you can compute:

\begin{align*} V_{TH}+ I_B^{'}\cdot R_{TH}+ V_{BE}^{'} + I_B^{'}\cdot\left(\beta+1\right)\cdot R_E&=V_{CC}\\\\ \therefore\quad I_B^{'}=\frac{V_{CC}-V_{TH}-V_{BE}^{'}}{R_{TH}+\left(\beta+1\right)\cdot R_E} \end{align*}

Given your values, I get $I_B^{'}\approx 9.6\:\mu\textrm{A}$.

The start of shallow entry into saturation occurs right when $V_{BC}=0\:\textrm{V}$ or when $V_B=V_C$:

\begin{align*} V_C&=V_B\\\\ I_C\cdot R_L &= V_{TH}+I_B^{'}\cdot R_{TH}\\\\ \beta\: I_B^{'}\cdot R_L &=V_{TH}+I_B^{'}\cdot R_{TH}\\\\ \therefore \quad R_L &=\frac{V_{TH}+I_B^{'}\cdot R_{TH}}{\beta\: I_B^{'}}=\frac{1}{\beta}\left(R_{TH}+\frac{V_{TH}}{I_B^{'}}\right) \end{align*}

From which I get $R_L\approx 2130\:\Omega$.

Maximum gain for CE stage is VDD/0.026; the current is irrelevant (within reason).

Consider a 26 volt battery. You can operate at 1mA (thus 24Kohm allows 2 volts across the Vce, so bipolar is just barely out of saturation), or 10mA or 100mA, or 1uA (with 24,000,000 Ohm Rcollector)

• Yeah. It maxes out at $40\cdot V_{CC}$. But I think the OP had a different question. Or did I miss something? – jonk Oct 3 '17 at 4:23
• Indeed, the question was a very different one. – Bimpelrekkie Oct 3 '17 at 6:44
• Then I apologize for providing insight to the OP. – analogsystemsrf Oct 3 '17 at 16:28