I'm going to develop a camera utilizing the NanEye 2D image sensor. This has LVDS interface. I'm using a MCU for data processing that does not have LVDS interface, but it has SPI and I2C. Therefore I was thinking of using a FPGA for a bridge from LVDS-SPI. I want the camera to be battery-powered, so power consumption is a key element in the choice of FPGA to use.

I was wondering if some might have some inputs to what FPGA to use, eventually if it would be wiser to use ASIC. I'm considering using the Microsemi Igloo Nano, the Lattice Mach03 and the Lattice iCE40.

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    \$\begingroup\$ I don’t think it will be possible to “bridge” them. The camera provides a significant amount of data. It generates 10 bits * 250 * 250 * 42 FPS (minimum) = 26,460,000 bits/s. That is without control messages, i.e. just the data. \$\endgroup\$
    – user110971
    Oct 3, 2017 at 12:17
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    \$\begingroup\$ This is like bridging a footpath to an Interstate highway. \$\endgroup\$
    – user16324
    Oct 3, 2017 at 12:33
  • \$\begingroup\$ This is kind of possible but quite close to the limit. You need to decode the LVDS stream (find frame boundaries and line boundaries) and encode it into SPI stream. And you need to design your SPI protocol. As long as your FPGA has the memory for a line or two of image and enough high speed pins for LVDS then you are good. I would recommend BeMicro board for the start. Honestly, if your budget is not too tight, easiest way is to burn the micro controller as a soft core into the FPGA, too and you don't need to worry about SPI any more. \$\endgroup\$ Oct 3, 2017 at 14:17

1 Answer 1


It seems you are planning to bridge from a high speed interface (LVDS) to a low speed interface (SPI), which will not work without some compromise.
LVDS is used for high speed data interfaces, usually to transfer several hundred Mbps (Megabits per second) or more.
SPI is a rather slow interface, usually providing a data rate of at most a couple of Mbps.

If a reduced frame rate is acceptable you could use an FPGA to buffer a single frame which was received over the LVDS interface. The MCU can then read the frame over SPI at a much slower speed. After the frame was collected by the MCU the FPGA will buffer the next frame and so on. Of course a lot of frames will be lost while the MCU is reading the captured frame from the buffer. Note that this only works if the frames contain raw image date, i.e. not encoded yet.


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