This question is on the fence between RC and EE; as the design style is half a century old, I decided to ask the RC audience first.
Back in 1965, Soviet computer developers used a rudimentary HDL in the manufacturing documentation. Bitwise combinational logic looked quite understandable, with · for AND, + for OR, and an overbar for NOT.
The registers, however, were defined in a more cryptic way.
For example (converting Russian abbreviations to English but keeping all other notation as is for authenticity), a typical bit of the accumulator in the middle of the mantissa was defined as
14bRxAcc = C·[ShREn·15bRAcc + HoldEn·14bRAcc + ShLEn·13bRAcc] + [ShMant4En·18bRAcc + ReplEn·14bNextAcc]·C 14bRAcc = K·14bRxAcc
RxAccare the arrays of stored bits of the accumulator
ShLEn- shift right enable, hold enable, shift left enable
ShMant4En- shift mantissa by 4 bit enable,
ReplEn- replace enable
NextAcc- the new value of the accumulator
Kare the opposite phases of the clock signal.
Splitting the RxACC assignment into two ORed clauses expresses the limitation of 3 OR clauses per standard element.
Here we can see the sequential left and right shifters, and a faster (4 bit positions per clock cycle) mantissa shifter, plus assigning a computed value of the bit.
However, if we rewrite this to zero-delay Verilog
assign RxAcc = C & (ShREn & RAcc | HoldEn & RAcc | ShLEn & Racc) | (ShMant4En & RAcc | ReplEn & NextAcc) & C; assign RAcc = K & RxAcc;
it will not work, because at any moment either
K is zero.
It should be noted that the design was static; it was possible to single-step the CPU from the console.
My question is, what would be the corresponding Verilog definition of RAcc and RxAcc, taking into account that both of them could be used by the combinational logic?
Is it safe to assume that whenever
K is mentioned in a formula, the expression should be taken as a latch rather than an AND gate?