This question is on the fence between RC and EE; as the design style is half a century old, I decided to ask the RC audience first.

Back in 1965, Soviet computer developers used a rudimentary HDL in the manufacturing documentation. Bitwise combinational logic looked quite understandable, with · for AND, + for OR, and an overbar for NOT.

The registers, however, were defined in a more cryptic way.

For example (converting Russian abbreviations to English but keeping all other notation as is for authenticity), a typical bit of the accumulator in the middle of the mantissa was defined as

14bRxAcc = C·[ShREn·15bRAcc + HoldEn·14bRAcc + ShLEn·13bRAcc] + 
             [ShMant4En·18bRAcc + ReplEn·14bNextAcc]·C
14bRAcc = K·14bRxAcc
  • RAcc and RxAcc are the arrays of stored bits of the accumulator
  • ShREn, HoldEn, ShLEn - shift right enable, hold enable, shift left enable
  • ShMant4En - shift mantissa by 4 bit enable, ReplEn - replace enable
  • NextAcc - the new value of the accumulator
  • C and K are the opposite phases of the clock signal.

Splitting the RxACC assignment into two ORed clauses expresses the limitation of 3 OR clauses per standard element.

Here we can see the sequential left and right shifters, and a faster (4 bit positions per clock cycle) mantissa shifter, plus assigning a computed value of the bit.

However, if we rewrite this to zero-delay Verilog

assign RxAcc[14] = C & (ShREn & RAcc[15] | HoldEn & RAcc[14] | ShLEn & Racc[13]) |
                   (ShMant4En & RAcc[18] | ReplEn & NextAcc[14]) & C;
assign RAcc[14] = K & RxAcc[14];

it will not work, because at any moment either C or K is zero.

It should be noted that the design was static; it was possible to single-step the CPU from the console.

My question is, what would be the corresponding Verilog definition of RAcc and RxAcc, taking into account that both of them could be used by the combinational logic?

Is it safe to assume that whenever C or K is mentioned in a formula, the expression should be taken as a latch rather than an AND gate?


migrated from retrocomputing.stackexchange.com Oct 3 '17 at 15:30

This question came from our site for vintage-computer hobbyists interested in restoring, preserving, and using the classic computer and gaming systems of yesteryear.

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    \$\begingroup\$ Now. thats realy fascinating. Is there any way to learn more about? Could it be that it's a RTL based language like KARL or AB(E)L not a free form HDL? But nonetheless, this is not a RC question, as you are looking for information about todays Verilog, not any old machine or technology. It would be more apropriate in plain Stackexchange. Remember to mention the environment/compiler you use, as Verilog has some real evil manufacturer dependant quirks. (Oh, and if you'r a beginner here, think about using VHDL instead. Not only better defined, but for sure using a more classic style) \$\endgroup\$ – Raffzahn Oct 3 '17 at 10:55
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    \$\begingroup\$ This seems close enough to the scope of Retrocomputing until the second-to-last paragraph when you state your actual question - "What would be... Verilog". I'm migrating this to EE. \$\endgroup\$ – wizzwizz4 Oct 3 '17 at 15:29
  • \$\begingroup\$ @user2973400 I only have a scan of the manufacturing documentation, for example - ~70Mb. This is just the ALU, but I'd like to convert it to Verilog to be able to see how many clock cycles it took to execute various arithmetic operations and how accurate were the performance claims. \$\endgroup\$ – Leo B. Oct 3 '17 at 20:17
  • \$\begingroup\$ @LeoB. Quite interesting. Are you sure that it's a free form HDL language? For the timeframe of the 1960, RTL based HDL was state of the art, thus I wouldn't be surprised if the usage of a clock signal in a term inherently ties it to one edge. Furthermore in that timeframe these languages where mosty for documentation purpose. Generation and verification was rather rare. (And please, take a look at VHDL as it's way better suited to simulate and validate designs than Verilog) \$\endgroup\$ – Raffzahn Oct 3 '17 at 21:24
  • \$\begingroup\$ @Raffzahn It was free-form, but you're right, it was mostly for documentation. Although I've read somewhere that formulas were converted to board connection tables in a semi-automated way. \$\endgroup\$ – Leo B. Oct 4 '17 at 2:43

I can't answer how to do this in Verilog, but I think it's safe to say that C/K is being used here to control the propagation of a signal through a latch.

I think the original intent was very obviously for C/K to control a latch here. The implication then is that this HDL was made for sequential circuits and that it performed all assignments at the same time (i.e. it was 'clocked'). So new values of RAcc and RxAcc are calculated based on the previous values, then the new values are written to RAcc and RxAcc both at the same moment. The problem of either C or K being zero then doesn't occur.

To put it another way, this HDL appears to use a model where variable assignment means "deposit this value into this variable at the end of the current evaluation cycle", while variable reference/evaluation means "retrieve the value this variable had at the start of the current evaluation cycle".

To put it yet another way, variables in this HDL appear to have their own virtual latches clocked by the simulator clock. New values are fed into all variables at the same time (call them registers if you like), but the variables don't 'accept' the new values until the end of the simulation cycle. Having this register-like behavior built into the language makes it very easy to represent latches using this C/K idiom.

This register-like behavior for RAcc/RxAcc may be triggered by how they are declared earlier in the file, or this may be default behavior. I can't tell from the snippet shown. If it's default behavior then this language may have a special syntax that is used for combinatorial circuits when a value is desired to be stored/retrieved instantly.

Also note: this language may not have had an actual simulator program to go with it -- the "simulator" it was written for may have been the human mind. If this was intended to be a human language rather than a computer language then the rules of the language don't need to be rigidly specified -- you can rely on context and human understanding to make the meaning clear.

  • \$\begingroup\$ I've heard that a simulator program existed but in the manufacturing documentation the formulas were hand-written and the style was apparently more free-form. I could see signals named "⇆" and "⇇", for example. \$\endgroup\$ – Leo B. Oct 3 '17 at 20:22

Any logic that requires a two-phase (nonoverlapping?) clock is probably dynamic, in the sense that it relies on the fact that node voltages won't change between the ending of one phase and the beginning of the next.

Such logic can't be simulated with zero-delay logic, but the judicious use of certain kinds of delay can make it workable.

  • \$\begingroup\$ If RxAcc wasn't used anywhere else, I could have concluded that the code represents two back-to-back opposite phase latches which together constitute a D-flip-flop. Unfortunately, that's not the case. \$\endgroup\$ – Leo B. Oct 3 '17 at 20:08

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