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I get

Net SCL/SCK contains floating input pins (Pin U1.1-4,Pin U1.2-4)

as the only error after compiling the project but I don't know why. The clock signal as well as V+ is shared among the different channels. V+ doesn't rais an error probably because it's connected to the sheet's power port via an inductor.

What's wrong with the design?

enter image description here

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The problem was that the used harnesses in the design required a netlabel each. After that, there were no more compilation errors.

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