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I am using an eeprom M24C32-W from ST. Here is my schematic with VCC=3.3V. The write protection Write Control pin is connected to VSS and thus should be disabled. The address of the device is 0xA0 (or 0x50<<1) because the pins E1, E2, E3 are connected to VSS. schematic

And here is my write and read command: I want to write value 0xAA to address 0xF0 but I cannot manage to read back this value. This is what my logic analyzer measures at the pull-up resistors. write (top), read (bottom)

Here is what I have tried so far:

  • writing to and reading from different memory addresses: 0x0000, 0x00F0, 0x00FF, 0x0FFF, 0xFFFF,
  • different delays between write and read: 0ms (it failed), 10ms, 1000ms.
  • write to device, power down board, power up board, read from device.

None of those worked so far, I am running out of ideas.

EDIT: I have tried various clock speeds with no success: 100kHz, 10kHz, 1kHz. The EEPROM is the only device on the I2C bus.


Solved:

It was simply a faulty hardware problem. I switched the eeprom for a new one and now it works. Thank you all.

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    \$\begingroup\$ Where are you measuring? Note that 3.3kΩ might not be the optimal pull-up for your application. Try with a much lower SCL frequency. \$\endgroup\$ – Marcus Müller Oct 5 '17 at 11:59
  • \$\begingroup\$ Thanks, I tried the following frequencies: 10kHz (the one in the picture), 100kHz and 1kHz. I am going to try changing the value of the pull-up resistors. \$\endgroup\$ – user2131322 Oct 5 '17 at 12:05
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    \$\begingroup\$ Logic analysers can fool you as they simply show if you went through a particular voltage; try looking at the signals with a scope. \$\endgroup\$ – Peter Smith Oct 5 '17 at 12:34
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    \$\begingroup\$ When you read from address 0x0000 what value do you read back? Still 0xF7? \$\endgroup\$ – Steve G Oct 5 '17 at 13:26
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    \$\begingroup\$ It was simply a faulty hardware problem. I switched the eeprom for a new one and now it works. Thank you all. \$\endgroup\$ – user2131322 Oct 5 '17 at 14:12
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You say it's a write protection pin, implying that asserting it prevents writes. Note that the pin name is written with a bar over it in the schematic. That means negative logic. Tying it low therefore asserts its function. If it is truly a write protect pin, then you are preventing writes by tying it low.

Since you didn't provide a link to the datasheet, I'll leave it to you to check what the function and polarity of the pin really are.

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    \$\begingroup\$ Thank you for your answer. The datasheet says: "If the addressed location is Write-protected, by Write Control (WC) being driven high, the device replies with NoAck, and the location is not modified. If, instead, the addressed location is not Write-protected, the device replies with Ack." The device replies with ACK (see the screenshots of the logic analyzer), therefore the location should have been modified. Sorry for not providing a link, I have not enough reputation to add another link to my question. \$\endgroup\$ – user2131322 Oct 5 '17 at 12:08

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