# Verilog Code Optimisation

I have recently become involved in FPGA design and I am just testing out some new Zync SoC hardware. I have followed a tutorial online to blink some LED's however I have modified it to blink all the LED's at different rates. My code is as follows and describes a potential 8 element LED counter:

//  Simple LED logic
// reg [28-1:0] led_reg2 [8-1:0]; // 28 bit wide, 8 element memory
reg [28-1:0] led_cnt_0; // 29 bit LED counter
reg [27-1:0] led_cnt_1;
...

always @(posedge sys_clk_i) begin // on every positive edge of system clock
if (!sys_rstn_i) begin // if the system is reset
// led_reg2{8-1:0} <= 28'h0; // failed attempt to describe resetting an 8 bit bank of registers to 0
led_cnt_0 <= 28'h0; // reset the LED counter
led_cnt_1 <= 27'h0;
...
end
else begin
led_cnt_0 <= led_cnt_0 + 28'h1; // increment counter
led_cnt_1 <= led_cnt_1 + 27'h1;
...
end
end

assign led_o = {led_cnt_0[28-1],led_cnt_1[27-1],led_cnt_2[26-1],led_cnt_3[25-1],led_cnt_4[24-1],led_cnt_5[23-1],led_cnt_6[22-1],led_cnt_7[21-1]};


My code does as desired and they blink at rates equal to 125e6 / 2^n - However, I am not satisfied with the layout of my code and the syntax, considering Verilog is designed to solve such problems of this nature.

My question is:

What is the correct/suitable syntax of such a problem? I have made attempts to solve this by making a 28 bit wide, 8 element register, however I don't know how to correctly control it. I have spent quite a while looking for similar problems and syntax's but have been unable to implement it correctly. I also think a trial and error approach to this is not the way forward, as this is not simply programming.

Additionally could anybody recommend suitable reading material to learn and practise Verilog, I am familiar with the structures etc, through lecturers a few years ago but have no clue with regards to the implementation.

Many thanks.

• You realise that led_cnt_1[26] and led_cnt_0[26] will be identical right? Same for led_cnt_2[25] and led_cnt_1[25] and led_cnt_0[25]. And so on and so forth. – Tom Carpenter Oct 6 '17 at 18:37
• So why not simply: assign led_o = led_cnt_0[27:20]? – Tom Carpenter Oct 6 '17 at 18:39
• (This is my first practical investigation into something on an FPGA) Thinking about this further it would be better to create a a single 29 bit counter and tap off the lines of the flip flops onto the different LED lines. This way you could get different blinking rates, however how would you reset the state of the LED, could you introduce a buffer flip flop ? – Renegade243 Oct 7 '17 at 17:54
• In your attempt to describe resetting led_reg2, you can use SystemVerilog syntax, led_reg2 = '{default:'0}; simply. But it depends on what FPGA synthesizer you use. – jclin Oct 10 '17 at 22:41