1
\$\begingroup\$

I am designing a 2 layer PCB for an LED module and need advice on EMC/EMI. I know EMI is more to do with fast rise and fall times and not frequency but I will post details anyway. The PCB will have a 5V regulator switching at 400 kHz, several switching LED drivers at frequencies between 600-900 kHZ and the microcontroller clock (no crystal oscillator) will be at 32 MHz. Data signals will be in the range of 100 kHz. We have had EMC compliance issues in the past on other PCBs where especially the clock signal caused EMI that violated the toughest European standards. So I am trying to use all the design options available to pass EMC requirements.

However, we also want to keep costs down and go with a 2 layer PCB if possible. The bottom layer will be a ground pour. The top layer will have DC power trace to feed power into all components. It will have all signal traces, LED power traces, and the rest will be filled in with a ground pour.

My question relates to via stitching. I have heard it can be used to reduce EMI, but to be honest I don't have alot of experience in this department. Even at 10 times the clock frequency (320 MHz) the wavelength is 0.9 meters, which is more than 3 times the length of the PCB. So my questions are as follows:

1) Will it help to do via stitching here in your opinion?

2) If it will help, since I only have 2 layers and cannot do a complete GND pour on the top layer, can I run a GND trace around the entire perimeter of the top layer and run all the vias along that trace? There will also be a ground pour on the top layer but this is a fairly densely populated board and the ground pour will cover only a fraction of the top layer. Will this trace around the perimeter on the top connected to GND work as a Faraday cage like via stitching is supposed to, or am I confused?

3) Since wavelength is 3 times the length of my PCB, can I just space the vias 2mm apart or so? Or will spacing them really close also cause issues? Can you recommend any appropriate spacing for the vias?

4) If you have any other suggestions for minimizing EMI please do share them with me.

Thank you for any help you can give.

\$\endgroup\$
  • 1
    \$\begingroup\$ Four question in one is likley to attracy Close due to too broad. Can you "lighten" up the block of text with some example pictures? \$\endgroup\$ – winny Oct 7 '17 at 7:11
2
\$\begingroup\$

On a two layer board, via stitching is probably not that helpful. The two most important things to reduce EMI:

  • make sure the ground plane is continuous below the power traces, so the return path is as close to the power trace as it can be. On a two layer board, this means that crossing power connections will be difficult and should be avoided if possible. Probably one of the least bad, but still bad ways:

Crossing a power trace

  • filter the power supply near the ICs so high-frequency components don't reach the longer traces (i.e. decoupling caps, and possibly some inductors as well)
\$\endgroup\$
0
\$\begingroup\$

To minimize radiation, draw out the various RETURN paths for the currents and make those narrow (out I and return I are close together) loops.

To minimize radiation, you need the same potential on both ends of a piece of GND foil. Thus at least stitch the ends of GND regions to the backside plane.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.