1
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i have a problem with this code, because in the RTL simulation, the output Cookie appears as StX. I don't know why this is happening since i don't know verilog well.

Can someone help me?

module dispenser(
CLOCK, SReset, 
SBCD, Cookie, valor,
reciba 
); 

//Port declaration
input CLOCK; 
input SReset; 
input [3:0] valor;

output reg reciba;
output reg [3:0] SBCD;
output reg Cookie = 0;    

always @(*)
        if( valor >= 4'b1000) 
          begin
            Cookie = 1; 
             SBCD = valor - 4'b1000;
             reciba = 1; 
          end
        else 
          begin
            Cookie = 0;
            SBCD = valor;
            reciba =0 ;  
          end
endmodule

and this is my testbench

`timescale 1 ns/ 1 ns
module vendingMachine_tst();

   //Parameters

   parameter TCK = 20; // clock period in ns
    parameter CLK_FREQ = 1000000000 / TCK; // Frequenzy in HZ

   //general purpose register
    reg eachvec; 

    //Internal wire and reg declaration 
    reg [3:0] TB_Un_US;
    reg [3:0] TB_Dos_US;
    reg [3:0] TB_Cinco_US;
    reg TB_Clock; 

    wire [3:0] TB_SBDC;
    wire TB_Cookie; 

    vendingMachine vM1(

      .Un_US(TB_Un_US),
      .Dos_US(TB_Dos_US),
      .Cinco_US(TB_Cinco_US),
      .SBCD(TB_SBDC),
      .Cookie(TB_Cookie),
      .CLOCK(TB_Clock)

    ); 

initial                                                
begin                                                  
// code that executes only once                        
// insert code here --> begin  
   TB_Clock <= 0;                         
// --> end                                             
$display("Running testbench");                       
end                                                    
always                                                 
// optional sensitivity list                           
// @(event1 or event2 or .... eventn)                  
   #(TCK/2) TB_Clock <= ~ TB_Clock; 
initial begin                                                  
// code executes for every event on sensitivity list   

//Caso 1: El cliente entrega justo el precio de la galleta 
    #0     TB_Un_US <= 4'b0001;
   #6000  TB_Dos_US <= 4'b0010; 
   #60000 TB_Cinco_US <= 4'b0101;


//El cliente supera el precio de la galleta 
 // #0   TB_Un_US <= 4'b0001;
//  #60   TB_Un_US <= 4'b0001;
//  #600  TB_Cinco_US <= 4'b0101;
//  #6000 TB_Dos_US <= 4'b0010;
//
//
////El cliente no completa el precio de la galleta 
//
//   #0   TB_Dos_US <= 4'b0010;
//  #6000  TB_Un_US <= 4'b0001;
//  #600000 TB_Un_US <= 4'b0001;





 #(TCK*300000) $finish ;
#(TCK*300000) $finish ;       
@eachvec;                                                    
// --> end                                             
end                                                    
endmodule
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  • \$\begingroup\$ What is the value of valor that you're feeding in? \$\endgroup\$ – Dave Tweed Oct 7 '17 at 0:16
  • \$\begingroup\$ @DaveTweed it's here electronics.stackexchange.com/questions/333091/… but SBCD always seems to be 0000 and i don't know what i'm doing wrong \$\endgroup\$ – Mel J Oct 7 '17 at 1:18
  • \$\begingroup\$ Oh, so this is essentially a duplicate question, then. \$\endgroup\$ – Dave Tweed Oct 7 '17 at 1:52
  • \$\begingroup\$ @DaveTweed i had to ask this separately because the output here is different from the other one \$\endgroup\$ – Mel J Oct 7 '17 at 1:53
  • \$\begingroup\$ But the underlying issue is exactly the same -- you haven't stated what the inputs to the module are. Show us your test benches! \$\endgroup\$ – Dave Tweed Oct 7 '17 at 10:30