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There's been much talk on other Q&A threads on how to connect decoupling capacitors to an IC, resulting in two completely opposite approaches to the problem:

  • (a) Place decoupling capacitors as close as possible to the IC power pins.
  • (b) Connect the IC power pins as close as possible to the power planes, then place the decoupling capacitors as close as possible, but respecting the vias.

Figure from Complete PCB Design Using OrCad Capture and PCB Editor by Kraig Mitzner, showing via and decoupling capacitor placement for one of the power pins; although adjacent power pins could be connected with two parallel traces to either vias or decoupling capacitors to reduce inductive loops for return currents even more

According to [Kraig Mitzner], option (a) is preferable for analog ICs. I see the logic behind it, as the inductance of the via and the decoupling capacitor form a low pass LC filter that keeps noise away from the IC's pins. But according to [Todd H. Hubbing], option (a):

[...] sounds like a good idea until you apply some realistic numbers and evaluate the tradeoffs. In general, any approach that adds more inductance (without adding more loss) is a bad idea. Power and ground pins of an active device should generally be connected directly to the power planes.

As for option (b), [Kraig Mitzner] (the author of the above figure) says that it is preferable for digital circuits, but he does not explain why. I understand that in option (b) the inductive loops are kept as small as possible; but still, they allow switching noise from the IC to get quite easily into the power planes, which is what I want to avoid.

Are these recommendations correct? What exact reasoning are they based on?


EDIT: consider that the via from the IC leads to the capacitor and vias are kept as short as possible. They are shown in the figure as long traces only for illustration purposes.

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    \$\begingroup\$ At lower frequencies it won't matter much, and at high frequencies odd things happen, however, I'd prefer option A in all general cases for one reason alone. In option B the current in the trace between the via and the capacitor actually goes from near zero to a spike on switching and has to reverse at the end of a switching operation to recharge the capacitor. \$\endgroup\$ – Trevor_G Oct 7 '17 at 12:40
  • \$\begingroup\$ The other option not shown here is to put the power plane via under the IC. Where layout constraints allow it, this allows equidistant placement of the via and capacitor to the power pin. \$\endgroup\$ – Polynomial Oct 7 '17 at 13:47
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Running some basic simulations with exaggerated values it is apparent that you end up trading off spike height vs ring height.

enter image description here

With circuit A you get less spike at the IC Vcc pin and more ring, and with circuit B, the opposite is true.

Note the current in the trace to the capacitor in circuit B though, it reverses.

The other option you have not shown is to put the power plane via under the IC so the trace lengths are equal. This gives you the best of both worlds as shown in the third plot. Again though the current in the cap line reverses.

From those graphs I'd actually say circuit A, is better for digital since spurient edges are more problematic than ripple, and circuit B is better for analog. Ultimately C is best. But when it comes to terms like "better", opinion comes into play.

Ultimately though, either way, you need to keep the capacitor and via as close to the pin using minimal traces between them to minimize the trace inductance. For example using tight pad/via combination as indicated Peufeu's answer.

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  • \$\begingroup\$ Thank you for your simulations and insight. However, I'm now even more confused than before regarding whether (a) or (b) are better for analog and digital respectively. Your reasoning is the exact opposite of that of Kraig Mitzner. Also, I wanted to ask why is it so bad that the current reverses. Thank you again. \$\endgroup\$ – andresgongora Oct 8 '17 at 21:02
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    \$\begingroup\$ You inspired me to run the same simulation, but watching the voltage at the power plane (I added one extra inductor between the via and the voltage source in your circuit, and measured there). Setup (a) has some ripple, but it is only around 10mv. Setup (b) has similar ripple, but I get a huge voltage spike of about -0.7V at very high frequency. You are absolutely right. (a) is much better for digital, as it keeps the HF noise away from the power distribution. Also, (c) which has the least inductance performs best for the IC, but doe not prevent HF noise from getting to the power distribution. \$\endgroup\$ – andresgongora Oct 9 '17 at 10:19
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    \$\begingroup\$ I agree with Trevor's results. Option (a) is better for digital circuits. \$\endgroup\$ – Guill Oct 12 '17 at 21:53
  • \$\begingroup\$ @Guill Ignoring opcion (c), two independent traces, and considering only (a) and (b): Trevor's result imply that Mitzner and Hubbing (authors cited in the Q) seem then to bee wrong, as (a) appears much better than (b); intuitively as well as in simulation. However, I believe there is much more to this and the reason they both propose (b) over (a). Afterall, one of them works for Orcad... Is there any other source I can go to? \$\endgroup\$ – andresgongora Oct 16 '17 at 8:45
  • \$\begingroup\$ @Trevor_G I have accepted your answer as it seems thoroughly reasoned and the simulations help a lot. I'm still a bit confused about why the end-result contradicts the other (for me authoritative) authors. In any case, I'll follow your lead and will play around with simulations to see what happens :) Thank you \$\endgroup\$ – andresgongora May 30 '18 at 7:48
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For lowest inductance, place the via to ground plane on the side of the cap instead of at the end of a skinny trace. You can put two vias, one on each side, it is even better.

enter image description here

(read the source)

Now, considering the circuit shown, the IC is in SOP or SSOP package, which means there is more than 5nH bondwire and leadframe inductance inside the package. One extra nH of trace inductance in the power line won't matter. If this is a digital chip, optimum plane decoupling will be achieved with the footprints on the right of the picture, and you can connect the IC's power pin to the cap's pad.

If this is a sensitive analog chip on a digital plane, then adding a resistor and/or a ferrite before the cap si a much better idea.

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  • \$\begingroup\$ Imagine then that in: (a) I connect the via as close as possible to the IC lead, and right next to it the decoupling capacitor; and that in (b) I do exactly the same but the other way around. Now the traces are as short as possible as shown in your figure (minimum inductance). Now, which configuration is better for keeping the power planes as decoupled from switching noise as possible? That is where I get really confused. Thank you :) \$\endgroup\$ – andresgongora Oct 8 '17 at 20:37

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