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I'm trying to build a counter with a-sync reset, that will be shown on the 7-segment display on the fpga board. I saw a few posts about my problem:

"near text "if"; expecting endmodule"

But still I can't understand why I'm getting that error, I know that I am missing an important rule, but I can't figure it out.

module up_counter(
input clk,rst,  
output segA, segB, segC, segD, segE ,segF , segG, segDP);
reg [3:0] BCD;

always @(posedge clk);
    reg [7:0] SevenSeg;
    if (BCD==4'h9) begin 
        BCD <= 4'h0;
        SevenSeg = 8'b11111100;
    end else if (rst==0) begin
        BCD <= 4'h0;
        SevenSeg = 8'b11111100;
    end else begin
        BCD <= BCD+4'h1;
        always @(*)
           case(BCD)
              4'h0:SevenSeg = 8'b11111100;//0
              4'h1:SevenSeg = 8'b01100000;//1
              4'h2:SevenSeg = 8'b11011010;//2
              4'h3:SevenSeg = 8'b11110010;
              4'h4:SevenSeg = 8'b01100110;
              4'h5:SevenSeg = 8'b10110110;
              4'h6:SevenSeg = 8'b10111110;
              4'h7:SevenSeg = 8'b11100000;
              4'h8:SevenSeg = 8'b11111110;
              4'h9:SevenSeg = 8'b11110110;
           default: SevenSeg = 8'b11100000;
           endcase
    end

assign {segA, segB, segC, segD, segE ,segF , segG, segDP} = SevenSeg;

endmodule

This "always" addition came after , I read that case and if statments need to come with always,but this didn't help. always @(*) case(BCD) Furthur more, i tried to put an "always" before the : if (BCD==4'h9) begin But then I got the same error:

"near text "always"; expecting endmodule"

I feel so limited, because at this moment every time I had an "if" , I get an error, so I'm missing here a serious and basic rule. Thanks a lot,I really appriciate your help.

Thank your all for your help, I think I did , every imporve you gave me, and this is the improve code:

module up_counter(
input clk,rst,
output segA, segB, segC, segD, segE ,segF , segG, segDP);
reg [3:0] BCD;
reg [7:0] SevenSeg;

always @(posedge clk)
begin
if (BCD==4'h9) begin 
   BCD <= 4'h0;
   SevenSeg = 8'b11111100;
end else if (rst==0) begin
   BCD <= 4'h0;
   SevenSeg = 8'b11111100;
end

else begin
   BCD <= BCD+4'h1;
   case(BCD)
     4'h0:SevenSeg <= 8'b11111100;//0
     4'h1:SevenSeg <= 8'b01100000;//1
     4'h2:SevenSeg <= 8'b11011010;//2
     4'h3:SevenSeg <= 8'b11110010;
     4'h4:SevenSeg <= 8'b01100110;
     4'h5:SevenSeg <= 8'b10110110;
     4'h6:SevenSeg <= 8'b10111110;
     4'h7:SevenSeg <= 8'b11100000;
     4'h8:SevenSeg <= 8'b11111110;
     4'h9:SevenSeg <= 8'b11110110;
     default: SevenSeg <= 8'b11100000;
endcase
end
end
assign {segA, segB, segC, segD, segE ,segF , segG, segDP} = SevenSeg;

endmodule

It did resolve the problem I had, but now, I get only 8 in the 7-segments display, is there any more rules Im missing.

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  • 1
    \$\begingroup\$ Without proper indenting, your HDL is much harder to read than necessary. \$\endgroup\$ – Araho Oct 7 '17 at 14:05
  • \$\begingroup\$ My wild guess is that your end if (rst==0) begin was meant to be an else if. \$\endgroup\$ – Polynomial Oct 7 '17 at 14:16
  • \$\begingroup\$ Thank you for the addvice, but that wasn't the problem, the "else" fell when i pasted, and organized the code. \$\endgroup\$ – albert1905 Oct 7 '17 at 14:22
  • \$\begingroup\$ Remove the ; from the end of the always line. \$\endgroup\$ – The Photon Oct 7 '17 at 15:04
  • \$\begingroup\$ What is at the end of the line that it tells you about that shouldn't be there? \$\endgroup\$ – Tom Carpenter Oct 7 '17 at 15:04
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I see two problems:

  1. The semicolon at the end of the first always line means the whole if structure that follows isn't inside the always block.

  2. You have a second always block nested insider your first one. There's no need to do that. Since you already are inside an always block, a multiplexer will be inferred from your case statement even without another always.

    The always @(*) construct is used when you want to produce a combinatorial multiplexer --- meaning you want to be able to access the unlatched multiplexer outputs. Since you're immediately latching the mux outputs here, there's no need for this.

  3. You can't (AFAIK, but I'm not up on the latest Verilog revisions) declare new signals (reg or wire declarations) inside an always block. Move your declaration of SevenSeg to the top of the module.

Style note: Use begin and end inside every always, even if you will only have one statement in the block. It makes it easier to follow the code, and avoids mistakes when you edit the code later.

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