what are these or gates for?

why do you need the or gates at the end of this circuit? cant you just tie all the would-be-inputs of the or gates together instead? also, what would be an example when you need to use or gates instead of tieing the outputs together?

thank you and sorry for my bad english • Are you trying to fry the totem-pole outputs? – Ignacio Vazquez-Abrams Oct 8 '17 at 1:00
• i think it would be a higher current if multiple were high, right? – parzival Oct 8 '17 at 1:05
• RTL isn't used much anymore. Try looking at a modern digital logic technology instead. – Ignacio Vazquez-Abrams Oct 8 '17 at 1:12
• en.wikipedia.org/wiki/Logic_family – Ignacio Vazquez-Abrams Oct 8 '17 at 1:30
• @parzival - You supplied a logic diagram which may be intended to use a modern logic family e.g. TTL (or variant) / CMOS (or variant). However you linked to an RTL gate schematic. It may help if you give more context e.g. (a) Why did you link to an RTL gate, and not TTL or CMOS? (b) Who designed that main logic diagram? (c) How is the RTL OR gate which you linked in a comment, related to the overall design e.g. do you intend to use RTL logic to implement that whole logic diagram? (d) Is this a school / university assignment (and if so, which logic families have you learned about so far)? – SamGibson Oct 8 '17 at 4:06

Boy that's a nasty comment discussion happening, sadly you can't thumb down comments that are incorrect (such as Don Joe's).

Onwards to the question at hand, tying outputs together. In the comment section you guys seem to love setting outputs to the same logical value, that's all fine and dandy. But so far none of you have tripped over the major problem.

What happens when one gate is outputting a logical zero and another gate is outputting a logical one? You'll get two transistors burning, one transistor that is trying to make the output high and another transistor trying to make the output low. If the transistors have equal $R_{d_{on}}$, also known as the resistance of the transistor while it is conducting, then the output will be inbetween of high and low.

So if a logic high is 5 V and a logic zero is 0 V, then the output will be 2.5 V. The resistances of the transistors will most likely be in a couple of ohm's range, if they are like in the 74ls series. Let's assume both transistors have an $R_{d_{on}}$ of 5 Ω. The power lost in the form of heat in one of the transistors will be $P=\frac{V^2}{R} = \frac{5^2V}{5 Ω} = 5W$. One, if not both of the transistors will let out a magic smoke.

TLDR; Transistors will burn up.

• Hi - "But so far none of you have tripped over the major problem." - Actually Ignacio highlighted the problem in his first comment :-) Of course your answer (describing totem pole (push-pull) outputs) is correct for standard TTL & CMOS family logic gates. However it makes an assumption which appears to be false for this OP. The OP has supplied a link to an RTL gate which is not "totem pole" and IMHO would not cause the problems you describe. Or does your answer apply to RTL as shown in the OP's link, and if so, how? – SamGibson Oct 8 '17 at 2:37
• This is why I didn't try to write an answer - topic too broad, needing explanation of multiple logic families and their characteristics :-( And perhaps the OP is using out-of-date RTL schematics for a logic diagram which assumes standard TTL or CMOS family gates? The question seems to have plenty of opportunities for misunderstandings :-( – SamGibson Oct 8 '17 at 2:39
• @SamGibson The question is why or gates exists. It doesn't matter if it's TTL or RTL or DTL. The output of any gate will be driven by one or several transistors. And at some point one of the outputs will not coincide with the other outputs and you'll get crappy outputs. – Harry Svensson Oct 8 '17 at 2:49
• "And at some point one of the outputs will not coincide with the other outputs and you'll get crappy outputs." We're not discussing "crappy outputs" but specifically the "letting out the magic smoke" that you described i.e. the totem pole problem. Look at the link in comments from the OP - that RTL gate can only "pull high" so the totem pole problem cannot happen, can it? That is why your answer, although correct for modern logic families, doesn't address that specific assumption by the OP. If you can explain how that RTL gate can cause the totem pole problem, that would be great, thanks. – SamGibson Oct 8 '17 at 2:53
• thank you for not getting mad/angry at me for asking such a "newbie" question, as answers to questions like this would usually be. usually people just call me stupid and i dont get an answer. thanks though. – parzival Oct 8 '17 at 17:37

At least on a theoretical basis, it's almost possible to do what you're asking.

To do it, you have to isolate the outputs of the two gates, so they either can drive the final output, but neither can interfere with the other. Roughly the simplest circuit that can to that is a pair of diodes: simulate this circuit – Schematic created using CircuitLab

The diodes basically let the values at A and B affect the output, but if A and B are driving opposite values, it prevents the "low" one from trying to pull the output voltage from the other to 0.

There are other kinds of circuits that allow you to do away with the diodes as well. The most common is an open collector/open drain circuit. In this case, you're typically dealing with an and instead of an or though. simulate this circuit

In this case (open collector/open drain) neither A nor B ever attempts to drive its output high. Rather, they're connected to ground, and either conducting or not conducting. The output is driven high by the voltage through the pullup resistor. If either Q1 or Q2 is conducting, it can sink all the current coming through the pullup resistor. The pullup resistor is spec'ed to only allow a fairly small current, so either A or B can safely sink all the current (and if both A and B are low, each will conduct about half the current, so it's even safer).

Obviously enough, this can be extended to more than two inputs (though if you try to go too far, you'll eventually run into problems--even when turned off, the transistors leak a little current, and if you get enough leakage in parallel, you eventually get to the point that it's no longer dependably held high even when none of them is conducting. One trivial cure for this is to use a smaller resistor to increase the current (but this obviously increases power usage).

Generally speaking with modern logic families you should only tie an output to one or more inputs unless they are 3-state outputs and you ensure that only one output is enabled at a time, or they are open drain/open collector outputs (in the latter case you need a pull-up resistor which will usually determine the power consumption when low as well as the time for the output to go from low to high.

The "wired or" name is actually assuming negative logic- any output low means that all outputs tied together are pulled low. The resistor pulls the outputs high. In your example case you could replace the right-hand column of AND gates with open drain NAND gates eg. 74HC03 (with a pullup resistor) and add a single inverter a after the wired-or node.

• Side note: ECL is one modern logic family that allows wired-OR connections at the outputs (anyway, it's nearly as modern as CMOS is). – The Photon Oct 8 '17 at 15:54

A Different Perspective

The 3 OR gates are used to combine 4 out of 16 "AND" combinations of 4 bits $Q1,Q2,Q3,Q4$ and their complements $\bar{Q1},\bar{Q2},\bar{Q3},\bar{Q4}$ to implement some function.

This is usually done easily with a Karnaugh Map in logic design, where the smallest scale integrated (SSI) logic used are the quad 2-in OR/NOR gates , quad 2-in AND/NAND , and in your case the hidden inverters.