5
\$\begingroup\$

I wanted to know if I can program CPLDs /FPGAs using C language? If so, is it commonly practiced? What are the steps and the required & tools for the same?

\$\endgroup\$
8
\$\begingroup\$

Generally you can. There is free SystemC for HLS(High Level Synthesis). HLS is getting more and more popular but what you have to remember is that you do not program CPLDs /FPGAs using C language, you rather describe hardware using C language. To make it work on real hardware you need vendor specific HLS tools.

In my opinion, writing synthesizable description in C is harder than in Verilog/VHDL but it is usually faster if you are familiar with the syntax and you follow some extra rules.

\$\endgroup\$
4
\$\begingroup\$

For FPGAs, yes. I don't think there are many tools to target CPLDs with C (although in theory it should be perfectly possible).

I may be talking heresy here, but (to me) the advantage of C-to-gates is that you can run an awful lot of your algorithm development and verification in pure-C (using your normal C development environment, and well understood software tooling/debuggers...) and once it is working to your satisfaction, target it to the FPGA.

Then you only have to validate the C-to-gates transformation (ie the tool) in simulation and hardware. If you write your algorithm in HDL, you have to verify the algorithm in very slow simulation, and then verify and validate your implementation in hardware (and/or even slower gate-level simulation).

You may have to iterate for performance (but you probably had to do that post-synthesis anyway even in HDL, unless you were very good at HDL optimisation... and I contend that after a few months you can be very good at C-for-gates optimisation and then not iterate as much either)

\$\endgroup\$
  • \$\begingroup\$ You can also validate an HDL-plausible algorithm as a C program, and then re-express it in an HDL. \$\endgroup\$ – Chris Stratton Oct 10 '17 at 18:10
  • \$\begingroup\$ Generally speaking, CPLDs are too small to target with HLS tools. \$\endgroup\$ – duskwuff Oct 10 '17 at 18:29
  • \$\begingroup\$ @ChrisStratton - you can yes. But then you have to verify that your HDL implementation matches the C each time it changes. If I validate the C-to-gates tool sufficiently, I can gain enough confidence to skip that step. Also I don't need to employ HDL engineers to do the translation or, even worse, find those rare engineers (like me :) that like playing with both! \$\endgroup\$ – Martin Thompson Oct 12 '17 at 19:26
  • 1
    \$\begingroup\$ If you want to run an algorithm expressed best in C, why not use hardware custom designed and specifically optimized to run C? I hear such things are called CPUs. \$\endgroup\$ – Cuadue Oct 12 '17 at 21:24
  • \$\begingroup\$ @Cuadue - I'm more concerned about verification than expressing algorithms. I can express a signal processing algorithm in a variety of languages. C allows me to verify that it works reasonably efficiently (by taking advantage of these CPU things you've heard of :). If I choose the right algorithm to express I can then target it at much lower cost&power hardware and still meet my hard-real-time goals. \$\endgroup\$ – Martin Thompson Oct 13 '17 at 17:42
2
\$\begingroup\$

There are two main ways to do this: one is with HLS where you write a description of a high level algorithm in c and it gets translated to HDL or a netlist. HLS is not really applicable for a complete design though, usually just a few pieces. The other way is to put a soft CPU on the FPGA, and then program that in C. Some FPGAs also contain hard CPU cores (Zynq has ARM cores, various Virtex chips have PowerPC cores) and those can certainly be programmed in C.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.