# Propagation delay in asynchronous circuit

Consider the circuit shown below where delay of each flip flop is 10ns and delay of each AND gate is 5ns each. What is the total propagation delay ? My Attempt:-

1) Consider that initial state i.e Q0Q1Q2 = 000 . So, after 10ns (5 + 5), we get inputs for all flip flops.

2)Now when we apply the clock to 1st flip flop (T0), it produces output after 10ns which acts as an input for T1.

3)After 10ns, T1 produces output in 20ns and activates T2. But by 15ns, output of 1st AND gate reaches simultaneously to T1 flip flop and 2nd AND gate and 2nd AND gate produces output in 20ns (15 + 5).

4)Now T2 takes another 10ns to produce output Q2 at 30ns (20+10).

So total propagation delay should be 30ns according to me.

But the answer is 30+5+5 = 40ns.

Please can someone tell me where am I going wrong ?

In your first step itself you assumed that the flipflop inputs are stable at 10 ns. But it’s not the case.

Say the input to 1st flipflop changes at t=0. Because of this input, one input of 1st AND gate will be affected at 0 ns, and the other input will get affected only after 10 ns because of the delay caused by T0. So the output of AND gate can change at 5 ns as well as at 15 ns. And you have to consider time taken for last transition.

Hence T1 will be getting a stable input only at 15 ns. So it will be producing a stable output only at 25 ns.

Similarly, the next AND gate output will be stable only by 30 ns. Hence the final output by 40 ns. So the propagation delay is 40 ns.

Propagation delay is the is the maximum time taken by a circuit or system to give a stable correct output after applying an input.

Here the paths available from input to output and corresponding delays are:

1. Input-A1-A2-T2-output : 20 ns
2. Input-A1-T1-T2-output: 25 ns
3. Input-A1-T1-A2-T2-output: 30 ns
4. Input-T0-T1-T2-output: 30 ns
5. Input-T0-A1-A2-T2-output: 30 ns
6. Input-T0-T1-A2-T2-output: 35 ns
7. Input-T0-A1-T1-T2-output: 35 ns
8. Input-T0-A1-T1-A2-T2-output: 40 ns

So the output can change at 20 ns, 25 ns, 30 ns, 35 ns and at 40 ns because of the input applied at 0 ns. Hence the valid stable output comes only after 40 ns. Hence 40 ns is the propagation delay here.

• I assumed that all inputs to flip flops are stable at 10ns at the beginning because we have Q0,Q1 and Q2 inputs (which are initial states) available at the beginning. So as the inputs are available at the beginning, it's just the matter of 10ns (5 + 5) for the inputs to propagate to the respective flip flops.Is my reasoning correct ? Also, AND gates provide inputs to the flip flops for next clock cycle right (I mean preparing inputs for the flip flops so that they can work properly in next clock cycle). Oct 10, 2017 at 21:08
• @RajeshR my answer is valid only if the flipflops are level triggered. If the flipflops are edge triggered, then the answer can be 30 ns. But before that you have to mention that what is connected at the clock input of 1st flipflop.. Oct 11, 2017 at 5:07
• How will the answer vary if it's edge triggered ? Oct 28, 2017 at 2:53
• @RajeshR if it’s edge triggered then flip flop will be sensitive only to clock edge. Whatever be the input when clock edge arrives, that will be sampled and corresponding output will be produced. So at 20 ns, the clock edge arrives at T2 and output will be given at 30 ns Oct 28, 2017 at 4:08
• @Zephyr if it’s level triggered, then only at 40ns, you will get the stabilized output. Output at 30 ns can be wrong. But if it’s edge triggered, then output comes to some value at 30 ns, it won’t change till 30 ns after the next clock edge arrives. So after 40 ns also the output which came at 30 ns will be remaining there. The answer at 30 ns with edge triggered can be different from what you will get at 40ns with level triggered flipflop, but will be stable. Oct 30, 2017 at 17:03