For general purpose PCBs that consist of an MCU (simple 8-bit, 20MHz), switching vreg (1.5MHz), and perhaps some SPI and I2C clients (such as sensors, wifi, gps modules, etc), what are recommended and typical baseline capacitors recommended to place near the power supply pins of each component?

I realize some ICs provide some recommendation on their datasheets, but many of them don't.

Assume, that the maximum inter-IC frequency is on the order of MHz (perhaps 1-4MHz at the most). Although it also matters that the actual transistor switching frequency inside these chips is equally (perhaps more) important.

I've seen references of adding a few capacitors at each IC, differing by "decade capacitance". In the past, I've typically just used 10uF in parallel with 0.1uF, MLCC capacitors, which seems to have worked. However, I'd like to know if there are other recommendations. How about adding a 1uF or a 0.001uF in parallel as well?

I suppose the answer to this question depends on trace length, possible noise sources, IC characeristics, etc...but assume general/typical/average case.


3 Answers 3

  1. Place a decoupling capacitor near every power supply pin of each digital IC, if at all possible.

  2. Typically, this should be 0.1 uF or higher ceramic multi-layer chip capacitor (MLCC), in the smallest package your assembler is comfortable working with. For your scenario I'd recommend 0402, but 0603 would also be fine if you are doing hand assembly.

    Choose parts with decent over-temperature and over-voltage stability. Typically this means choosing the "X7R" type.

  3. Place higher-value bulk bypassing capacitors around the board, but not necessarily at each power pin.

I've seen references of adding a few capacitors at each IC, differing by "decade capacitance".

I agree with this rule. Spreading the capacitor values by more than a decade increases the risk of running into anti-resonance, which causes very high power supply impedance at certain frequencies. This is explained in a very good Murata app note.

However, I'd like to know if there are other recommendations. How about adding a 1uF or a 0.001uF in parallel as well?

In most scenarios, adding lower-value capacitors in the same size package as your primary decoupling capacitors will be counter-productive, as it will push the primary decoupling capacitors farther away from the power supply pins and increase their effective series inductance.

  • \$\begingroup\$ Does "decade difference" mean the difference between a 10uF and a 1uF, or is it 10uF and a 0.1uF? \$\endgroup\$
    – Adam B
    Commented Oct 10, 2017 at 17:08
  • \$\begingroup\$ @AdamB, a decade is a factor of 10, so 10 uF and 1 uF are one decade apart. 1 uF and 0.1 uF are one decade apart. \$\endgroup\$
    – The Photon
    Commented Oct 10, 2017 at 17:15
  • \$\begingroup\$ Is it typically better to use 10uF + 0.1uF, or 1uF + 0.1uF for most/typical examples of the subject of this question? Assume larger capacitors are already placed elsewhere on the PCB (i.e. near VREG and near connectors, etc.). \$\endgroup\$
    – Adam B
    Commented Oct 12, 2017 at 3:44
  • \$\begingroup\$ I prefer not to use capacitors in parallel that are more than a decade apart in value. So 0.1 uF and 1.0 uF is okay. 0.1 and 1.0 and 10.0 uF is okay. But 0.1 uF and 10 uF is not okay. For details why, read the Murata app note I linked to. \$\endgroup\$
    – The Photon
    Commented Oct 12, 2017 at 4:15
  • \$\begingroup\$ Upvoted ;) Paralleling multiple values is only useful for closely coupled power/ground planes on a big board. For DIY builds of a board with a small micro which is the case here, the best is to get a tape of 100x 1µF 0603 caps, quantity discount for the win, spray them around, one per power pin, that'll last for several projects... \$\endgroup\$
    – bobflux
    Commented Nov 10, 2017 at 11:18

Picking the capacitors is a useless endeavor if you ignore the inductance of the PCB, inductance of Vias, inductance between GND and VDD (preferably planes). Oh, and inductance of the capacitors. And inductance of the MCU package, if you have a choice.


With rise time,t (ns) related to BW (GHz) f=0.35/t for 10 ~ 90 %

Choose caps with SRF > BW Use Ferrite beads for improved low noise for ADC and DAC’s.

The bottom choice is best. enter image description here

Low ESL have a shorter L/W ratio. Beware of anti-resonant combinations with ESL of large e-caps or high ESR , use ceramics . Decouple each LSI chip.


Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.