2
\$\begingroup\$

I use one SPI bus from CPU to two FPGAs with different (i.e. individual) CS signals.

The CPU and first FPGA are powered up, and the second FPGA is unpowered.

When I send SPI signals to both FPGAs, the second (unpowered) FPGA shorts the shared SPI signals and first (powered) FPGA can't recognize the low amplitude signals.

Why this can happen and how to fix it?

\$\endgroup\$
3
  • \$\begingroup\$ Hi - If you have time, please can you check my edits to your question, and make sure that I have included the details of your question correctly. If I have made any incorrect change, you can edit it yourself, or you can tell me where it is wrong and I will try to improve my edit. \$\endgroup\$
    – SamGibson
    Commented Oct 11, 2017 at 4:59
  • \$\begingroup\$ Thanks for edit! All good, but I think main keyword "short" are better then only "affect". "affection" I think is so blurry. \$\endgroup\$
    – Ilia
    Commented Oct 11, 2017 at 5:28
  • \$\begingroup\$ Thanks, OK, I have changed that part to specifically state that the SPI signals were "shorted". :-) The reason that I used slightly less definite words in my earlier edit, was because if they were really shorted (to ground), then the signal amplitude would be (very close to) zero volts. In your circuit, with the second FPGA unpowered, I would expect to see SPI signals of a few tenths of a volt (e.g. perhaps between 0.3V to 0.6V) and therefore not strictly "shorted". However it is your story, so I'll edit the story however you want. :-) Thanks again :-) \$\endgroup\$
    – SamGibson
    Commented Oct 11, 2017 at 5:43

2 Answers 2

2
\$\begingroup\$

Although some parts of the story are not completely clear to me, the overall situation seems to be a known problem.

Why this can happen

Connecting signals to an unpowered IC (in your case the second FPGA) is usually outside of that IC's specification (with a few exceptions, typically on ICs which are specifically designed for bus isolation - see below). Check that device's datasheet, to see if the input voltage specification mentions Vcc / Vdd, or a specific voltage. If it mentions voltages referenced to Vcc / Vdd then think about what that means, when the device is unpowered.

If you need help interpreting the datasheet of your FPGA, then supply a link to its electrical specifications page, and we can try to find the relevant part for you.

If you do connect signals to such an unpowered IC, then this tends to try to power the unpowered IC through the ESD protection structures on those signal pins of the unpowered IC. However the IC was never intended to be powered through its signal pins, those signals may be unable to supply the necessary current to power the IC (of course, they were never designed to do that) and so the signal voltages may go out-of-specification, the IC may not be powered correctly (since this method of supplying power was never intended) and a variety of incorrect behaviour can be seen. See the questions & answers to these previous topics, for similar problems:

Isolate microcontroller from board and use other one

Unpowered devices on I2C/SPI bus

how to fix it?

Use appropriate bus isolation ICs, which are designed to allow one part of a bus to be unpowered, without affecting other devices on the powered part of the bus. For example, TI and Analog Devices (among many other manufacturers) make such devices, depending on your speed, current, package, cost, availability and other requirements.

In some cases, the 74LCX125 (which has a specification that allows for active input signals, even when it is unpowered) is an example of a type of IC which can be used to buffer signals to an unpowered device i.e. the 74LCX125 and the unpowered device would be connected to the same power rail, and therefore become powered or unpowered together.

\$\endgroup\$
5
  • \$\begingroup\$ Thanks, this is a good description. And I'm very sorry for unreadable story. I'll try to learn English better. \$\endgroup\$
    – Ilia
    Commented Oct 11, 2017 at 3:47
  • \$\begingroup\$ @ИльяА - You're welcome. Your story was not unreadable and I'm not criticising your English (my Russian skills are zero!), but I just wanted to highlight that I cannot be sure that I understood you completely e.g. about which signals you found were being "shortened" (you probably translated a word that means "shorted"?). The shared SPI signals would be affected by the unpowered FPGA, as I described. However a CS signal which went from the CPU only to the powered FPGA, should not be affected. I hope that is clear? \$\endgroup\$
    – SamGibson
    Commented Oct 11, 2017 at 3:54
  • \$\begingroup\$ yes, this is what I meant. \$\endgroup\$
    – Ilia
    Commented Oct 11, 2017 at 4:01
  • \$\begingroup\$ Great :-) Good luck! (удачи тебе!) \$\endgroup\$
    – SamGibson
    Commented Oct 11, 2017 at 4:04
  • \$\begingroup\$ A quick and dirty hack if you are just trying to get something up without a board respin is to add resistors (try a couple of k) between the unpowered part and any signal lines that may be driven from elsewhere. Not as good as a proper tristate buffer, but something that can often be hacked onto a prototype more easily. \$\endgroup\$
    – Dan Mills
    Commented Oct 11, 2017 at 12:40
1
\$\begingroup\$

You could use a voltage translator chip that is guaranteed to behave well (not load the inputs) with a supply (of two) absent.

In some cases you might be able to just use series resistors on SCK and data and /CS to your 2nd FPGA but it's not the best practice.

It's also possible that certain FPGA input structures (those designed to be tolerant of input voltages higher than the relevant I/O supply) may not exhibit this issue but read the specs very carefully with regard to permissible input voltages. You did not do that which is why you are seeing this problem- probably there is an absolute maximum input voltage of Vddio + 0.3V or something similar and you are violating that spec.

\$\endgroup\$
1
  • 1
    \$\begingroup\$ Thanks. I think about level converter IC, but at first I wanted to understand why this is happening. Unfortunately before I did not attach importance to the Vddio +0.3V parameter. And now, after your answer, I realized what it means. \$\endgroup\$
    – Ilia
    Commented Oct 11, 2017 at 4:04

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service and acknowledge you have read our privacy policy.

Not the answer you're looking for? Browse other questions tagged or ask your own question.