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I've been looking around the web about placement and proper net routing of decoupling capacitors for ICs. In this example I have a pic micro-controller using internal clock at 80MHZ, with the decoupling caps placed closed to it on the same layer (top). The only difference between them is the way the nets are routed.

This is a four layer PCB:

  1. ------Top Signal-------
  2. ------Return Plane-----
  3. ------Power Plane------
  4. ------Bot Signal-------

What I've found from my searches is that everyone agrees on placing the decoupling cap close to the IC and on the same layer when possible, also if going to planes vias should be as close as possible to cap pads and use as small a cap size as possible. but then when it's about making the connection with the IC pads there are different versions. Of course on my design I have the room to move the caps around and place them wherever I want.

I've read things like the following:

  1. Sequencing the caps, so that power comes in first through the cap and then a trace to the IC pad. (Example 1)
  2. No vias in between IC pins and cap to join with a trace, vias must be on outsides. (Example 1 and 3)
  3. If more that one decoupling capacitor, the smaller cap should be closer to the IC pin. (Examples 1-4)
  4. No traces between cap and IC pads when possible, always preferred method is to use vias when power planes are used. (example 4)

I hope that someone can shine some light on this topic. If I where to pick one, it would be Example 4. Caps are reversed, opposing vias are close which should minimize inductance loop. Decoupling cap placement

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marked as duplicate by Wesley Lee, Tut, laptop2d, winny, PeterJ Oct 15 '17 at 11:23

This question has been asked before and already has an answer. If those answers do not fully address your question, please ask a new question.

  • \$\begingroup\$ Traces look a bit thin. Why would you want to put a cap near the IC and then 2 vias in series? \$\endgroup\$ – Wesley Lee Oct 11 '17 at 14:48
  • \$\begingroup\$ From the list of four things that you read, do #1, 2, and 3. #4 is bull unless there is no need for a decoupling capacitor. \$\endgroup\$ – DerStrom8 Oct 11 '17 at 15:21
  • \$\begingroup\$ My preference is #1 - gets the components closest to the actual pins - You're trying to provide a reservoir of charge available to the chip's die, you want the minimum inductance in the wire from the closest cap to the die - on both the power and ground wires so that the charge can arrive as fast as possible to the die usually on clock edges \$\endgroup\$ – Taniwha Oct 12 '17 at 23:26
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Did you know that vias add a few nH of parasitic inductance to your capacitor? Even the leads on body of the capacitor add inductance. Inductance is the enemy of decoupling, it is the reason why we use decoupling capacitors in the first place (so there is no voltage drop from the the wire from the voltage regulator).

So the less inductance you have the better decoupling you'll get, go find a PCB trace\via calculator and calculate the impedance of the capacitor. They look like the picture below. And if you add vias, the impedance dip gets worse as the cap filters high frequencies less.

enter image description here

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