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I have an output status signal, that is needed only for simulation. But Vivado 2017.2 doesn't like that it not physically connected (unconstrained):

[DRC UCIO-1] Unconstrained Logical Port: logical ports have no user assigned specific location constraint (LOC). This may cause I/O contention or incompatibility with the board power or connectivity affecting performance, signal integrity or in extreme cases cause damage to the device or the components to which it is connected. To correct this violation, specify all pin locations. This design will fail to generate a bitstream unless all logical ports have a user specified site LOC constraint defined. To allow bitstream creation with unspecified pin locations (not recommended), use this command: set_property SEVERITY {Warning} [get_drc_checks UCIO-1]. NOTE: When using the Vivado Runs infrastructure (e.g. launch_runs Tcl command), add this command to a .tcl file and add that file as a pre-hook for write_bitstream step for the implementation run. Problem ports: ready.

So is it possible to leave it unconnected? Or alternatively, that is used only in the simulation but not in synthesis and implemention? I know, I could separate sources for simulation, but is not convinient, especilly if I need to make corrections as result of the simulation.

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  • \$\begingroup\$ What about associating a formal in a port map to the reserved word open? Btw. you error message makes no sence, because VHDL and Vivado don't care about unconnected output ports. Furthermore, all ports need to be constrained! Please show us your entity declaration and instantiation. Your question doesn't contain a minimal verifiable problem. \$\endgroup\$ – Paebbels Oct 12 '17 at 12:20
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    \$\begingroup\$ Putting a -- pragma synthesis_off comment before the simulation only port and -- pragma synthesis_on after it might work. You could also remove the port and use VHDL 2008 aliases to access the signal in simulation \$\endgroup\$ – ks0ze Oct 16 '17 at 13:49
  • \$\begingroup\$ @Paebbels By physical connection I meant assigning an physical output pin, which made over constraints \$\endgroup\$ – Andrey Pro Oct 16 '17 at 17:23
  • \$\begingroup\$ @ks0ze It is called -- synthesis translate_off in Vivado, but that is what I need. Your hint would be actually the best anwser to this question. \$\endgroup\$ – Andrey Pro Oct 16 '17 at 17:25
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You don't have to make different sources. You can use a constant in one package, naming it "MODE", and if MODE = SIM you make an if-generate that adds your simulation-only output, otherwise it is not generated. You only have to remember to update that package accordingly, either for simulation or bitstream generation.

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  • \$\begingroup\$ You don't need a generic. The environment (simulation or synthesis) can be determined by is_x('X'). \$\endgroup\$ – Paebbels Oct 16 '17 at 21:21

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