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I am trying to analyze this circuit, the cap is initially charged to 3 V, the supply is 3 V. The NMOS threshold voltage is 0.7. Next the voltage at gate steps from 0V to 3V, what would be the voltage at source of MOS?

This is the circuit:

enter image description here I am unable to understand the role of Cap here, Could I consider it floating?

Thanks,

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  • \$\begingroup\$ If Vx is open, then the cap will discharge to the mosfet threshold voltage while the gate is still at 0V \$\endgroup\$
    – BeB00
    Commented Oct 12, 2017 at 23:53
  • \$\begingroup\$ In fact, I think as long as there is a voltage source connected to the gate, and the voltage is between -∞ and +6V, the cap will still discharge to 0.7V (not sure about the 6V, could be lower) \$\endgroup\$
    – BeB00
    Commented Oct 12, 2017 at 23:56
  • \$\begingroup\$ I think the final voltage should be 2.3V at Vx \$\endgroup\$
    – sarthak
    Commented Oct 12, 2017 at 23:57
  • \$\begingroup\$ Ooh actually, the cap will discharge to the higher of (Vgate-vdd) and (Vthreshold), which in this case is 0.7V \$\endgroup\$
    – BeB00
    Commented Oct 12, 2017 at 23:59
  • \$\begingroup\$ @sarthak yes, since the cap is at 0.7V \$\endgroup\$
    – BeB00
    Commented Oct 13, 2017 at 0:00

1 Answer 1

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Let's consider the circuit at time t<0. Here's the circuit and the current flow:

enter image description here

At time less than 0 the gate source voltage is +3V. Hence \$V_x\$ is at -3V. Therefore the drain-source voltage becomes 3--3=6V. The transistor then starts off in saturation and the current flows all the way to ground. Note that in saturation, we have \$I_D=k/2.(Vgs-0.7)^{2}\$. As capacitor discharges Vgs decreases further and further until it gets to 0.7V. At this time the mos is off and the capacitor has +0.7V across it.

Now the supply makes a transition to +3V at time t=0. Therefore the voltage on the gate rises to 3V. Applying KVL, we get: -3V + 0.7 + Vx=0 or Vx=2.3V.

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