# Sequence of capacitor's charge and discharge in voltage quadrupler

I was taking a lecture about diode and ended up stuck on understanding voltage quardupler below:

• On first positive (+) half cycle, C1=VM.

• On first negative (–) half cycle, C1 is discharged, and together with induced voltage provide C2=2VM.

• On second positive (+) half cycle, C2 is discharged and with induced voltage provide C1=VM and C3=2VM.

• On second negative (–) half cycle, C1 and C3 are discharged and with induced voltage provide C2=2VM and C4=2VM.

And here are my questions:

1. On first positive half cycle, can induced voltage VM charged on capacitor C3 or C2 instead? If diode D1 is conducted, then D3 should be conducted as well as it shares same bias. Is this due to KVL or currents tendency to flow on short circuit then opened capacitor due to constant voltage difference?

2. On first negative half cycle, how to set up KVL? After C1 is discharged and C2=2VM, I tried to set up KVL just to make sure. But since C1=0, I could only find -VM and 2VM from induced voltage and C2. What did I do wrong?

3. On second positive half cycle, how did 2VM from C2 transferred to C3? Although D1 and D3 are currently conducted, that doesn't mean reverse bias can now pass through the conducted diode like forward bias do. Did current somehow passed through D2 from C2 to C3 despite capacitor's polarization? Or did it went through inductor without affecting C1?

4. On second negative half cycle, how did voltage got distributed C2=2VM and C4=2VM? Why not C2=3VM and C4=VM if total 4VM is supplied from C1 and C3 with induced voltage?

I did asked to professor, but he kept saying that current and voltage behave differently, which I couldn't understand what he was trying to say here.

Your operational cycle definition is the simplified model which is used to understand how the final state of multipliers ends up at the voltages they do.

In reality, as you imagine, while ramping up it is not that simple and takes more than a few cycles to reach the final charge state.

On first positive half cycle, can induced voltage VM charged on capacitor C3 or C2 instead?

No.... or rather, only a little. Because D1 is on, the applied voltage across the C2-D3-C3 path is limited to D1's forward voltage. As such, though some current will flow through C2 and C3, it is not much.

Re the second half cycle: Note in your description you mentioned ..

On first negative (–) half cycle, C1 is discharged, and together with induced voltage provide C2=2VM.

This is where the simplified model breaks down. Since C1 is discharging during the charging of C2, the final voltage on C2 with not reach 2VM on the first cycle. It will be closer to 1.5VM. On subsequent cycles C2 will top up the 2VM.

With no losses at each cycle the voltage on C2 will be... (1+1/2)Vm, (1 + 3/4)Vm, (1 + 7/8)Vm, (1 + 15/16) Vm.... ad. infinitum

The remainder of the multiplier is just more of the same.. and each capacitor charges up at a slower and slower rate due to the discharging effects.

Note in a real multiplier there are also losses due to leakage and circuit resistances. As such there is a limit to how far this circuit can be extended. Eventually the amount you charge each cycle approaches than the capacitors intrinsic leakage rate. The circuit will not gain any voltage past that point.