3
\$\begingroup\$

I'm new to this forum and to microelectronics, my apologies if I don't give all relevant information.

I'm trying to use a FAN3214TMX low-side MOSFET gate driver (datasheet).

Input is provided by a Raspberry Pi GPIO, which delivers a 200 us pulse of 3.3 V in a nice rectangular shape. VDD is provided by batteries (3 x 4.5 V in series). Measurements were performed with a picoscope against GND. The whole setup is on a breadboard.

I expected a rectangular pulse of 200us with 13.5 V at OUTA. Instead I got the signal below.

Any help is much appreciated!

gate_driver_output

circuit diagram 2.2 nF dummy capacitor circuit on breadboard

UPDATE: I soldered the IC onto a SMD development board, glued two SMD ceramic caps (1 uF and 10 uF) on top of it and connected them to GND and VDD. It works as it should, even with the ca. 10 cm each of air wiring: enter image description here

With a total gate charge of 2.2 uC I get a rise time of ca. 200 ns. Problem solved! Thanks guys.

\$\endgroup\$
  • \$\begingroup\$ I've added an answer explaining the areas of concern which I suspect are causing your problem. It would be helpful to take a step back, and for you to explain why you are trying to use a MOSFET gate driver? As you are new to microelectronics, it's an unusual first project. Perhaps there is a different, easier, approach which someone can recommend for you, when you give more details about your actual "goal", and the reasons for your current plan. \$\endgroup\$ – SamGibson Oct 14 '17 at 15:55
  • \$\begingroup\$ Please edit both images to 1) Crop out the useful part of the schematic and 2) Zoom in or use two oscilligrams eith different time scales. \$\endgroup\$ – winny Oct 15 '17 at 8:14
  • 1
    \$\begingroup\$ @Sam The overall project goal is to produce 1 ms current pulses of 10-20 kA amplitude at < 10 V in order to deliver 20 J of energy to a sample. This primary current loop is driven by supercapacitors and is switched by 10 power-mosfets in parallel. Switching already works with a crude amplifier I made from two smaller mosfets. In oder to shorten switching time, I wanted to use the dedicated mosfet gate driver. I didn't mention this because I already isolated the problem at the oszillating gate driver, and to reduce complexity. \$\endgroup\$ – Matt Oct 15 '17 at 19:33
6
\$\begingroup\$

The device seems to be oscillating. I doubt that the single 10uF decoupling capacitor shown in the schematic will be enough, depending on its type, ESR & physical location. That is because the device requires large pulses of current to operate its fast internal switch and high-current output drivers.

Notice that the datasheet has specific guidelines on the type, physical location, and value of the decoupling capacitors (plural) that it recommends. Your schematic does not meet those recommendations:

Vdd Bypass Capacitor Guidelines from FAN3214 datasheet

(Vdd Bypass Capacitor Guidelines from FAN3214 datasheet)

The datasheet also includes an example test circuit showing multiple capacitors, as required by those guidelines:

Test circuit example from FAN3214 datasheet

(Test circuit example from FAN3214 datasheet)

Also notice the recommendations in the datasheet section called "Layout and Connection Guidelines". Since you explained that this prototype is on a breadboard, and the IC is an SOIC-8 package, you must be using some kind of adapter. It will be difficult to meet those recommendations in that case:

Layout and Connection Guidelines from FAN3214 datasheet

(Layout and Connection Guidelines from FAN3214 datasheet)

Please add a clear, in-focus photo of the breadboard (clearly showing the MOSFET gate driver itself, the wire lengths to each power supply, and the physical location of the decoupling capacitor etc.). Photo now added to question, thanks.

While you are testing without a real MOSFET attached to the output, adding a capacitor to simulate the gate capacitance of a MOSFET, between OUTA and GND, might help to reduce the oscillations by reducing the output rise/fall times - however that does not eliminate the concerns I've described above. If you can add a 2.2nF capacitor (as used for some of the datasheet specifications) between OUTA and GND, please report the results.


Update after breadboard photo was added:

Thanks for adding the photo, and adding background to the project as a comment.

After seeing the breadboard, my thoughts are summarised in the new answer from peufeu - the fast-switching gate driver IC simply won't work successfully using "air wiring" like that, for reasons including the inductance of those wires, the requirements for specific layouts of the current paths and lack of a local (i.e. within a few millimeters of the IC) decoupling capacitor.

Adding an SMD decoupling capacitor by gluing it onto the IC and connecting across Vdd and Gnd can only help, but that won't be enough on its own IMHO.

I've added some of the guidelines (i.e. strong suggestions) from the datasheet into my answer text above, so that readers can see them without having to download the datasheet.

I know you said that you want to avoid making a PCB for this. Unfortunately I see only two options to give a good chance of success:

  • design & make your own PCB; or
  • find someone else who is already selling a suitable, known-working MOSFET gate driver on a PCB.

There are further examples of layout recommendations here which may be helpful:

Infineon Application Note - Benefits of low side MOSFET drivers in SMPS

Fairchild Semiconductor presentation - Drive and Layout Requirements for Fast Switching High Voltage MOSFETs (However note that there appears to be an error on page 37 - the "good layout" and "bad layout" titles are *reversed!)

Then, as peufeu said, the MOSFET load also needs low-inductance design.

I realise this isn't what you want to hear, but I don't have a better conclusion.

\$\endgroup\$
  • 1
    \$\begingroup\$ I'm upvoting because you took the time to explain the current loops which are essential here. Also you can prototype it, but you need to use special low-inductance techniques, aka "ugly mode" with copper tape and kapton tape. Example: electronics.stackexchange.com/a/331541/13616 \$\endgroup\$ – peufeu Oct 16 '17 at 10:38
  • 1
    \$\begingroup\$ Thanks ;) in OP's case considering the kA current, big burly copper bars seem inevitable, so a low-inductance construction would probably involve a drill press and some craftsmanship... for a one-off it sounds doable though, but requires "knowing what one is doing" ! \$\endgroup\$ – peufeu Oct 16 '17 at 12:05
  • 1
    \$\begingroup\$ @SamGibson Thanks for your detailed answer, I learned a lot more about inductivities. I consider my question answered. \$\endgroup\$ – Matt Oct 18 '17 at 8:20
  • 1
    \$\begingroup\$ @peufeu Thanks for the "ugly mode" links, very helpful. I'll use a SMD-prototyping board to make my next version of the circuit, I'll post the result here. \$\endgroup\$ – Matt Oct 18 '17 at 8:21
  • 1
    \$\begingroup\$ OK! Remember inductance is loop area, that is why traces or planes over a ground plane have much lower inductance than wires. For prototyping a bit of blank PCB provides the ground plane. You can even use wires for traces, if they're taped close to the ground plane it can work very well. \$\endgroup\$ – peufeu Oct 18 '17 at 8:31
2
\$\begingroup\$

After seeing the breadboard picture, I'm not surprised it doesn't work.

This chip is very fast (10ns rise time) and has very high di/dt (it drives several amps into a MOSFET gate with switching times in the nanoseconds) therefore it won't work with the huge amount of inductance you have on your breadboard, long wires and all. Remember e=L di/dt thus with di/dt in the 1A/ns range you need inductance in the low-digits nH range.

This needs a good layout, with a ground plane, and close decoupling capacitor.

In fact I am quite baffled you would even think it would have any chance of working with the breadboard picture you show. The inductance of the wires will be at least 50 nH. This can't work. Also you're using through-hole ceramic caps for decoupling... this won't work...

LIkewise your 10kA switching project can't work without a proper low inductance design. You can post a question about that if you need help.

\$\endgroup\$
0
\$\begingroup\$

Your output is 12 cyces in 1uS, or 80 nanoseconds, or 12MHz. The LC product for resonance at 12MHz is 175 uH*pf.

The 10uF is 10^7pF, thus 175/10,000,000 = 1.75/ 100,000 (uH) or 1/60,000 uH or 0.06nanoHenry, well under a mm of wire.

I suspect the onchip well-substrate capacitance (1nF SWAG for 1amp powerdriver) will resonate with 0.175uH or 175nH or about 10cm of wire (that is 4").

Place a 0.1uF right across the VDD/GND pins of the powerdriver IC.

\$\endgroup\$

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.