I am trying to figure out the capacitance seen at each node, given that the source and drain diffusion capacitance is shared in the nmos stack. Given that the fingered layout uses a finger width of W=2 I want to try to find the capacitance at both B and N. I thought that based on the widths in the nmos stack the shared diffusion would be equal to (6+2)/2 unit C but I seems like I am wrong. I also thought that both N and B nodes would experience the same capacitance but I'm not sure. Can anyone explain why my analysis is incorrect?

CMOS gate in question


Node N has 6 + 6 of Nchannel

Node B has 6 + 6 of Pchannel, 6 of Nchannel, 12 of Pch gate and 2W (12?) of Nch gate.

No way are B and N of the same capacitance.

  • \$\begingroup\$ I believe that would be the case for a layout with unshared diffusion regions but in the case of a layout (with finger width W=2) would't the capacitance of both p and n network should be drastically reduced? \$\endgroup\$ – shiloh12 Oct 16 '17 at 6:07
  • \$\begingroup\$ Depends on whether the diffusions are shared. But that was not part of your questions. \$\endgroup\$ – analogsystemsrf Oct 16 '17 at 16:41

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