In sequential circuit block diagram ,it is said that some outputs are again feedbacked to inputs,after storing them in memory. But,where is that memory in sr latch.In sr latch ,it is seen that the output is directly taken to the inputs,and their is no memory.
Some of the inputs are taken from the outputs in your drawing, not the other way around. Left/Right direction in the drawing doesn't matter, signals always flow from outputs to inputs.
Since some of the inputs (one input from each NAND gate) are depending on the outputs of the NAND gates, it is sequential and with this particular configuration it has memory.