I know FETs have a Absolute max \$|V_{gs}|\$, and a max \$V_{ds}\$. So can we assume, say for an N type, that: $$\text{max}|V_{gd}| = V_{ds} + |V_{gs}|\\$$

  • \$\begingroup\$ Surrey it would be Vds - Vgs for an enhancement FET? \$\endgroup\$ Oct 16, 2017 at 1:10
  • \$\begingroup\$ I'm not sure if there is a physical reason that would be true, but my thought is that \$V_{gs}\$ is often \$\pm\$ and that \$V_{ds}\$ is positive by definition since a negative value would make the FET behave like a diode (I think, the ones I use, anyway). \$\endgroup\$ Oct 16, 2017 at 1:13
  • \$\begingroup\$ For MOSFETs the Vgs max is usually +/- 20v or even lower. Max Vds is usually 30V or more. So gate voltage must not exceed the drain voltage when at max Vds. \$\endgroup\$ Oct 16, 2017 at 1:25
  • \$\begingroup\$ That's true, but if you have a \$V_s=0\text{ V}\$, \$V_d=100\text{ V}\$, and \$V_g=-20\text{ V}\$, and your \$\text{max}[V_{ds}]=200\text{ V}\$, with the "usual" \$V_{gs}\$, are you safe? ---- I guess I'm asking about \$\text{max}[|V_{gd}|]\$ \$\endgroup\$ Oct 16, 2017 at 1:53
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    \$\begingroup\$ I did find a link from TI with a relevant comment indicating that Vgs or Vds would be exceeded before Vgd e2e.ti.com/support/power_management/power_stage/f/208/t/629840 \$\endgroup\$ Oct 16, 2017 at 2:27

2 Answers 2


First of all, the oxide layer that separates the drain/source from the gate in the source/drain-to-gate overlap regions1 is not thicker than the oxide layer over the substrate (i.e. where channel forms). That would require at least an extra step in the manufacturing process. Instead, in integrated IC MOSFETs, an extra thick-oxide "spacer" is then grown (as a lateral separator), but the breakdown voltage is still determined by the "thin" oxide layer in such overlap (and channel) regions.


In a planar MOSFET, i.e. typically found in digital and analog ICs, the MOSFET is symmetric. Therefore \$V_{GS,max} = V_{GD,max}\$ and \$V_{GS,min} = V_{GD,min}\$ (this latter formula is for negative gate-to-source or gate-to-drain voltages2).

Discrete/Power MOSFETs

Discrete/power MOSFETs are different, and conduction occurs vertically. There are many variants (V-MOS, U-MOS, etc.), but the principle is the same, so let's analyze one of them:

enter image description here

Don't be fooled by the symmetric design! This is not a conventional MOSFET! The source is both on the left and on the right! The drain is at the bottom!

The thin oxide layer still determines the low gate-to-source breakdown voltages.

Why is \$|V_{GD,max}|\$ much larger than \$|V_{GS,max}|\$ then?

For the sake of simplycity let's consider an nMOSFET only.

The drain is (almost3) always polarized positively with the source/substrate. Therefore there will be a depletion region in the drain-to-body junction. Since the body is p+ and the top part of the drain is n-, such depletion region will extend mostly in the n- layer. This will create a large voltage drop (which of course depends on \$V_{DS}\$) between the drain contact and the interface between the gate and the drain contact. Therefore the voltage between the gate and the very top part of the n- layer does not exceed the SiO2 breakdown voltage.

This (and not the different oxide thicknesses) determines the different \$V_{GD}\$ and \$V_{GS}\$ maximum ratings.

The weak point now becomes the body to drain junction breakdown voltage. By choosing the doping and the layer thicknesses (and also the "shape" of the regions, to avoid point effects), the \$V_{DS,max}\$ can be determined.


Planar MOSFETs (ICs) have maximum \$|V_{GD}|\$. In discrete MOSFETs, such value is larger than the maximum \$|V_{DS}|\$, hence no specification is given, as reaching such limit would imply that you already reached a catastrophic drain-to-body breakdown.


  1. There must be an overlap between source and gate (and drain and gate), to allow an efficient injection of charge. Othewise, there would be a very high series resistance (and the MOSFET would not work).
  2. The positve and negative breakdown voltages are not always necessarily the same value. This is due to the different barrier heights (i.e. different charge injection efficiencies) and different band alignments between the two electrodes with the silicon dioxide.
  3. You can have the drain at a smaller voltage with respect to the source, in a power nMOSFET. However, such difference will be at most "0.7V", because the body diode then starts conducting.
  • \$\begingroup\$ I think this is important information, but it's left me with even more questions. \$\endgroup\$ Oct 16, 2017 at 6:20
  • \$\begingroup\$ Which questions? I'll be back in few hours for further clarifications! \$\endgroup\$
    – next-hack
    Oct 16, 2017 at 6:28
  • \$\begingroup\$ Okay so: 1. The channel is being "built" in that small P-type junction touching the N-, N+ Contacts, and Oxide? 2. Why is drain less negatively doped than the body? Isn't the increase \$V_{breakdown}\$ of \$V_{gs}\$ just a result of the increased distance between the Gate and Drain? You mentioned that the depletion region created a large natural voltage differential, but what is "large" and why would this significantly impact \$V_{breakdown}\$, if \$V_{gs}\$ and the \$V_{depletion}\$ have the same sign, wouldn't that \$V_{depletion}\$ make it easier to breakdown? \$\endgroup\$ Oct 16, 2017 at 18:33
  • \$\begingroup\$ (this will be likely a multipart comment) 1. Yes, the channel develops just in that thin p-region (but it forms only close to the oxide, i.e. on the top). 2. The drain doping is smaller than the substrate for two reasons: a) so that the depletion region develops in the drain region and not in the substrate. This allows for a large voltage drop on the n- region (high VDS rating) and avoid punch-through (again, high VDS rating). b) the device is created from bottom to top. You have a n- substrate, and if you need to create a p-region, you must add acceptors (continues on the next comment) \$\endgroup\$
    – next-hack
    Oct 16, 2017 at 18:46
  • \$\begingroup\$ (continues) Adding acceptors to a n-substrate to form a new p layer is called doping compensation. This is reliably achieved only if the new doping (of opposite polarity) is much larger (e.g. an order of magnitude) than the original one. Vbd is increased because there is a large voltage drop (which of course depends on VDS!) in the n- region, even if no current is flowing (the drop is due to the depletion region). The depletion extention depends on the VDS. I mean that it is the large VDS (actually, VDB) that creates the depletion region (which "eats" most of the VDS). \$\endgroup\$
    – next-hack
    Oct 16, 2017 at 18:56

I did a small experiment with AO3401A which is trench technology mosfet, (if that matters). Well, it's P-channel, so it's not exactly matching your question. I think Vgd max question may arise for P-channel as it's sometimes used as a reverse polarity protection and so blocking large negative Vdg is potentially part of the design.

Absolute maximum ratings: Vds max = -30V Vgs max = +/- 12V

My setup:

  • Vg = V_in
  • Vd = Gnd
  • Source attached to a voltmeter (measuring Vgs).
Vgd = -V_in Vgs I_in
-12V 0V 0mA
-30V 0V 0mA
-37V -0.0001V 0mA
-37V -0.1V 0mA
-40V -0.2V 0mA
-42V -0.3V 6mA
-45V or so* -3V or so* few tens mA*
-46V burst short

Vds = Vgs - Vgd (it's positive - note that Vgs max is negative).

*I got nervous at higher voltage (grabbing safety glasses) and I didn't write down exact values.

So it seems that Vgd max could follow: $$ |V_{GD_{max}}|=V_{DS_{max}}-|V_{GS_{max}}| $$ ...analogous to your equation for N-channel type. This could mean that for AO3401A Vgd max is about +/-42V.

That's all I have. A little bit of measurement and speculation. Still, much to learn about semiconductor build fundamentals...

  • 1
    \$\begingroup\$ "Vi" seems named wrong \$\endgroup\$
    – Ben Voigt
    Jun 29 at 14:43

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