9
\$\begingroup\$

I'm working on an IoT board and it is all laid out (LTE, GPS, BLE, WIFI - 30mm x 30mm -- VERY TIGHT).

As a design concession, I have to use vias to route some of the RF signals. There's no other way to keep the board that small.

I've impedance matched and tuned several RF boards. I'm using the same PCB material, so I am confident the 50Ω traces will be correct. And I have a VNA to tune the matching network to the antenna.

However, what happens when the 50Ω traces hit a via?

Is there an known equation for impedance matching through vias?

Should I even worry about it if the traces are 50Ω?

I have a matching network from signal out on the IC to the antenna, so is it a moot point? Just use whatever via you want, and correct the impedance at the matching network?

\$\endgroup\$
11
  • 2
    \$\begingroup\$ It'll reflect for sure, I've got a feeling there's no way you can maintain the impedance with vias. You must accept some performance loss. How long are your traces? If they're just some millimeters/centimeters, you might get away with it... Edit don't expect that I know anything about the subject :| \$\endgroup\$ – PkP Oct 17 '17 at 15:37
  • \$\begingroup\$ The longest trace is around 15mm. \$\endgroup\$ – Leroy105 Oct 17 '17 at 15:38
  • 1
    \$\begingroup\$ Saturn PCB Toolkit has a via impedance tab \$\endgroup\$ – Matt Young Oct 17 '17 at 15:57
  • 1
    \$\begingroup\$ Please see this related question. One of the answers has a cool link on calculating via impedance by hand :) \$\endgroup\$ – bitsmack Oct 17 '17 at 16:18
  • 2
    \$\begingroup\$ @ThePhoton, Actually he did specify the frequency bands: LTE, GPS, BLE and WiFi. That's 1.8G, 1.2-1.5G, 2.4G and 2.4G. \$\endgroup\$ – PkP Oct 17 '17 at 18:31
6
\$\begingroup\$

However, what happens when the 50Ω traces hit a via?

The via can act as a capacitive or inductive discontinuity in the transmission line. It will make at least a small reflection.

Below 1 GHz, this discontinuity is usually too small to worry about unless you're doing something like precision radar work. Above 5 GHz, you'd generally want to carefully design your via to maintain impedance matching as well as possible. 1-2 GHz is kind of a messy middle ground where you might get away with an unmatched via and you might not. So you probably at least ought to make a best effort at designing a matched via.

First, you want to minimize any via stub. If you can, route from the top to the bottom layer, not from layer 1 to layer 3, for example. If you can't, expect a capacitive discontinuity from the stub. It's possible to "back-drill" the via to eliminate most of the stub, but that's probably not justified at 2.5 GHz.

Second, if you aren't routing between layers that share a ground plane (for example layer 1 and layer 3 might both use layer 2 as their ground plane, but layer 1 and layer 8 don't), then make sure there is a nearby path for return currents to move between the ground planes of the two signal layers. One nearby ground via is okay. Two or three is even better. If one layer uses a power plane as its reference, then place a bypass capacitor for that power net near your via.

Third, you can use a tool like the Saturn PCB tool (google it) to design the via diameter and antipad diameter around it as it goes through power and ground planes, to give the via a characteristic impedance matching your line.

Is there an known equation for impedance matching through vias?

There are at least heuristic formulas. Tools like Polar or the Saturn PCB tool can be used to find the via's characteristic impedance, which depends mainly on the via diameter and the antipad diameter.

Should I even worry about it if the traces are 50Ω?

At 15 mm trace length and 2.5 GHz, you're over 1/10 wavelength in trace length. It's probably a good idea to make controlled impedance traces, but it will probably not be too critical to get everything exactly right.

\$\endgroup\$
10
  • \$\begingroup\$ Thanks sir. I haven't actually built anything in the 2.5GHz range. I am re-laying out this board again (which is an agonizing 6 hour process), I see what you are saying with the layers order and vias. Unfortunately, I do have the signal going from bottom to top. Saturn PCB Tool -- thank heaven, I don't want to calculate that by hand based on a link I saw earlier. \$\endgroup\$ – Leroy105 Oct 17 '17 at 19:11
  • \$\begingroup\$ Top to bottom is good because there's no stub on the via. But slightly bad because you'll need to have return current paths also (assuming more than 2 layers total). If you have ground planes adjacent to both signal planes, that's really not a big deal. \$\endgroup\$ – The Photon Oct 17 '17 at 19:13
  • \$\begingroup\$ Yes, it's a 4 layer board (right now!). There is not an adjacent GND plane to the bottom layer. For the first turn, I should spin it as a 4 layer and see. I suspect this will take few turns of the board to get things nice and happy. \$\endgroup\$ – Leroy105 Oct 17 '17 at 19:21
  • \$\begingroup\$ Save your self the time and don't even try to go for a 4 layer board if the RF trace on the bottom doesn't have an adjacent ground plate below (or above, depends how you look at it). Maybe you should show the layout of the RF for a review here. \$\endgroup\$ – Mike Oct 17 '17 at 20:47
  • 2
    \$\begingroup\$ Tracks on layer 3, if they're parallel to the signal track on layer 4, could get some signal coupled from the signal track. Perpendicular tracks on layer 3 are not likely to cause a problem. If you have a power plane on layer 3, you can use that as the return path for your RF track, but you need to think carefully about how the return path connects to the source and load (and put bypassing near your vias as I discussed in my answer). \$\endgroup\$ – The Photon Oct 17 '17 at 22:09

Your Answer

By clicking “Post Your Answer”, you agree to our terms of service, privacy policy and cookie policy

Not the answer you're looking for? Browse other questions tagged or ask your own question.