I know things that happen every time clock ticks. Present state and inputs are delivered to the combinational circuits and it produces the outputs and the next state information and sends the next state to the memory elements. Then memory elements(e.g A SR flip flop) read the S and R signals and lock the Q on a new value based on them. The thing that I don't understand is what happens until the next clock? It seems that there's no apparent obstacle/isolation between the next state and the current(present) state in this time interval... Are they equal until the next clock? Of course still everything else make sense to me and this is not contradictory to anything I knew about memory elements and flip flops and etc... , because actually, at every clock-tick moment, information from memory elements are read from one epsilon moment before, and the combinational circuits have a delay too, so for a special moment the present state and the next state are different and are really what their names suggests, but in the middle of two clocks, my defective understanding says they should be equal... .
In a topology like this, the present state is read from memory and passed through combinational logic to compute a new state. Until the clock ticks, that new state is sitting at the write port of the memory waiting to be written. As soon as the clock ticks, the new state is written to the memory, and for a brief instant the present state and next state are equal. This brief instant is the propagation delay of the memory (time from clock edge to availability on read port) plus the propagation delay of the combinational logic. After this time, the NEW new state is sitting at the output waiting to be written, and the cycle continues.