# Multiple Transistors (FinFET) sharing a gate?

Transistors are among the most fundamental components of electronic devices, and that to produce transistors with better performance, FinFET transistors have been developed:

This allows for better control over the channel between the source and drain of the transistor. What is preventing us from using multiple transistors that share the same gate?

I believe that this could allow for some more complex/efficient analog design in circuits. Does it affect the electrical performance of the transistors?

My questions:

1. Is this design actually in practice?
2. If not, would it be beneficial for this design to be used when applicable?
3. How would this affect electrical performance, if the effect is not negligible?
• My recollection from my limited study of CMOS IC design is that having multiple channels intersect the same gate poly is a pretty standard design technique, so I don't know why it wouldn't work in the FinFET geometry, but I don't have an answer for you that's specific to FinFETs. Good first Q btw! – ThreePhaseEel Oct 20 '17 at 3:20

## 1 Answer

Since the channel width is determined by the height (and also by the thickness, which you want to keep small) of the fin, if you want a large W/L ratio (to achieve, for instance, a larger drain current), then you need to create multiple-fins finFETs, resulting in many finFETs in parallel.

In the picture above, the distance between drain and source (i.e. the width of the blue gate, along the fin axis) is channel length. The quantity $2\cdot H_{fin}+T_{fin}$ defines the channel width.

You might also want to share the gate (without connecting both the sources and drains in parallel) in other applications, such as memories or logic functions.

Here is a electron microscopy of many finFETs sharing the same gate.

As a last remark: I know that this would be quite difficult to render graphically, but in your picture, the thin dielectric layer, which separates the substrate from the gate, is missing!

• Ommision of the dielectric layer is quite common in images of finfets, I've found. I think it's to avoid making the complex 3d figure even more complicated? – Joren Vaes Oct 20 '17 at 9:27